• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.6
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• pp.52-65
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• 1978

Computer-aided design of color TV circuits has been tried using circuit analysis programs. Due to the complexity of colorplexed composite video signals of the color TV, conventional methods are difficult to apply in the color TV circuit design. This paper describes how to design Y video circuit, chroma cicruit, AGC circuit, and sync separator circuit of color TV using analysis programs.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1029-1032
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• 2000

A neuro-fuzzy based circuit to recognize circuit pat-terns is proposed in this paper. The simple algorithm and exemption from the use of template patterns as well as multipliers enable the proposed circuit to implement on the hardware of an economical scale. Furthermore, thanks to the circuit design by using current-mode techniques, the proposed circuit call achieve easy extendability of tile circuit and efficient pattern recognition with high-speed. The validity of the proposed algorithm and tile circuit design is confirmed by computer simulations. The proposed pattern recognition circuit is integrable by a standard CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2091-2096
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• 2013

This paper present a method of efficiency circuit design based on directed graph which was represented by tree structure relationship between input and output of nodes. In this paper, we introduce the concept of mathematical analysis based on tree structure which was designed by optimal localized computable circuit. Using the proposed circuit design algorithms in this paper, it is possible to design circuit which directed tree graph have any node number. The proposed method is more effective, regularity and extensibility than former method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.798-804
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• 2003

In this paper, We have designed an advanced circuits for controlling the Ink Nozzle of Printer Head We can fully increase the number of nozzle by reducing the number of Input/Output PADs using the proposed new circuit. The proposed circuit is tested with only 20 nozzles to evaluate functional test using FPGA sample chip. The new circuit architecture can be estimated. Full circuit for controlling 320 nozzles was designed and simulated from ASIC full custom methodology, then the circuit was fabricated by applying 3${\mu}{\textrm}{m}$ CMOS process design rule.

• Journal of Power Electronics
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• v.7 no.4
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• 전기의세계
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• v.28 no.9
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• pp.51-59
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• 1979

The forming and design method of D.C thyristor chopper circuit for DC Series motor control is suggested, ard the computation method of thyristor commutaing element's, value which makes it all the more important, is possible. Also the trigger circuit was dealt with. In this paper, in order to control the duty cycle, the duty time is kept on constancy and variable chopping frequency was adopted. By above mentioned circuit design method, the D.C thyristor chopper circuit was implemented and tested. In this circuit, the result of D.C motor control was good and reliable. The relation between the $K_{d}$ and the ratio of input-output current, or the characteristic of speed was varied lineary at the range 0.1 ~ 0.9 of duty cycle. This confirms the fact that D.C to D.C power conversion which is the merit of chopper control is operated most likely a transformer.ormer.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.521-522
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• 2006

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. The SIMULINK modeling was built in the frequency-time mixed domain whereas the Verilog-a modeling was built purely in the time domain. The simulated results of the two models were verified to show the same performance within the error tolerance. This top-down design method can provide the readiness for the transistor-level design.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.523-524
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• 2006

Successive approximation A/D converters have an advantage of small chip area and simple algorithm. We propose an improved non-redundant successive approximation register (SAR) which can be incorporated in successive approximation A/D converters. The proposed SAR validates the preset state as the $1^{st}$ reference voltage to the comparator. Two redundant clock cycles in the typical design could be eliminated in the proposed A/D converter.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.625-626
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• 2006

An Ultra low power super-regenerative oscillator was implemented with on-chip inductor and quench signal generator. The super-regenerative oscillator detects the signal level as low as -70dBm while consuming only 0.48mA at 1.5V supply voltage. These results indicate that the super-regenerative oscillator can be outstanding candidate the simple, ultra low power receiver design.

• ETRI Journal
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• v.44 no.5
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.