• Journal of Electrical Engineering and Technology
• /
• 제1권2호
• /
• pp.233-236
• /
• 2006

A 3-D numerical simulation of a buried-channel CCD (Charge Coupled Device) with a deep depletion has been performed to investigate its electrical and physical behaviors. Results are presented for a deep depletion CCD (EEV CCD12; JET-X CCD) fabricated on a high-resistivity $(1.5k\Omega-cm)\;65{\mu}m$ thick epi-layer, on a $550{\mu}m$ thick p+ substrate, which is optimized for X-ray detection. Accurate predictions of the Potential minimum and barrier height of a CCD Pixel as a function of mobile electrons are found to give good charge transfer. The depletion depth approximation as a function of gate and substrate bias voltage provided average errors of less than 6%, compared with the results estimated from X-ray detection efficiency measurements. The result obtained from the transient simulation of signal charge movement is also presented based on 3-Dimensional analysis.

• 한국광학회:학술대회논문집
• /
• 한국광학회 2000년도 하계학술발표회
• /
• pp.228-229
• /
• 2000

Buried channel JET-X CCDs (Joint European X-ray Telescope Charge Coupled Devices: EEV CCD12) with a deep depletion have been analyzed to provide an optimized condition for a charge storage and transfer. A maximum charge capacity has been found for the supplementary narrow channel by considering the potential distribution as a function of a mobile charge. Analysis for the depletion edges of JET-X CCDs have been successfully performed, showing good agreement with the depths estimated from X-ray detection efficiency measurements [1]. (omitted)

• Journal of Electrical Engineering and Technology
• /
• 제1권3호
• /
• pp.396-405
• /
• 2006

The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

• 한국재료학회지
• /
• 제29권7호
• /
• pp.408-411
• /
• 2019

ZTO/n-Si thin film is produced to investigate tunneling phenomena by interface characteristics by the depletion layer. For diversity of the depletion layer, the thin film of ZTO is heat treated after deposition, and the gpolarization is found to change depending on the heat treatment temperature and capacitance. The higher the heat treatment temperature is, the higher the capacitance is, because more charges are formed, the highest at $150^{\circ}C$. The capacitance decreases at $200^{\circ}C$ ZTO heat treated at $150^{\circ}C$ shows tunneling phenomena, with low non-resistance and reduced charge concentration. When the carrier concentration is low and the resistance is low, the depletion layer has an increased potential barrier, which results in a tunneling phenomenon, which results in an increase in current. However, the ZTO thin film with high charge or high resistance shows a Schottky junction feature. The reason for the great capacitance increase is the increased current due to tunneling in the depletion layer.

• 전자공학회논문지D
• /
• 제34D권12호
• /
• pp.31-38
• /
• 1997

A new CAD-compatible non-quasi-static (NQS) MOS transient model is presented. A new type of weighted residual method, the collcoatin method, is adopted to obtian an approximate ordinary differntial equation from the continuity eqation. Contrasting to the conventional NQS models, the new model can directly include the variatin of the depletion charge and the derived transient current sare expressed with only physically meaningful variables. The new model predicts transient behaviors reasonably well in the calculation including cutoff regions where the depletion charge rapidly changes.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
• /
• pp.155-158
• /
• 1988

The fabrication of devices using plans technology could lend to n serious degradation in the breakdown voltage as a result of high electric field at the edges. An elegant approach to reducing the electric field at the edge is by using field limiting ring. The presence of surface charge has n strong influrence on the depletion layer spreading at the surface region because this charge complements the charge due to the ionized acceptors inside the depletion layer. Surface charge of either polarity can lower the breakdown voltage because it affects the distribution of electric field st the edges. In this paper we discuss the influrences of fixed oxide charge on the breakdown voltage of the p+/n junction with field limiting ring(or without field limiting ring).

• 한국전기전자재료학회논문지
• /
• 제30권10호
• /
• pp.665-671
• /
• 2017

Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권4호
• /
• pp.361-366
• /
• 2013

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.

• Nuclear Engineering and Technology
• /
• 제29권6호
• /
• pp.451-458
• /
• 1997

Signal shapes from a closed-ended coaxial HPGe detector are investigated by numerical methods. The detector used in this study has a volume of 72 ㎤ with relative efficiency of 15%. The electric field and potential distributions in the detector are determined by solving the Poisson equation at the depletion and operating bias. Hence the time dependent signal shapes induced on the electrode are obtained from the energy balance consideration and tv solving the equation of motion for the charge carriers. For various initial positions of a charge carrier pair, the collection times of induced charge vary in the range of 70 - 404 nsec.

• 대한전자공학회논문지SD
• /
• 제40권6호
• /
• pp.379-383
• /
• 2003

Double-Gate MOSFET의 TSi변화에 따른 subthreshold 특성을 비교 분석하였다. Lightly-doped asymmetrical 소자의 경우에 symmetrical 소자에 비하여 subthreshold current가 TSi에 따라 급격하게 증가하는 현상을 발견하였으며 이는 낮은 depletion charge 때문에 TSi내의 전압분포가 linear한 특성을 갖는 것에 기인함을 밝혔다. 또한 이러한 현상을 설명할 수 있는 analytical equation을 유도하였으며 analytical equation 결과와 device simulation 결과를 비교하여 그 정확도를 검증하였다.