• Title/Summary/Keyword: Channel thickness

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Threshold and Flat Band Voltage Modeling and Device design Guideline in Nanowire Junctionless Transistors (나노와이어 junctionless 트랜지스터의 문턱전압 및 평탄전압 모델링과 소자설계 가이드라인)

  • Kim, Jin-Young;Yu, Chong-Gun;Park, Jong-Tae
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.12
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    • pp.1-7
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    • 2011
  • In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

  • Kim, Kwan-Young;Jang, Jae-Man;Yun, Dae-Youn;Kim, Dong-Myong;Kim, Dae-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.2
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    • pp.134-142
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    • 2010
  • A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

A CFD Analysis on DPF for the Removal of PM from the Emission of Diesel Vehicle (디젤차량 배기가스의 PM 제거에 관한 매연여과장치 전산해석)

  • Yeom, Gyuin;Han, Danbee;Nam, Seungha;Baek, Youngsoon
    • Clean Technology
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    • v.24 no.4
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    • pp.301-306
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    • 2018
  • Recently, due to the increase in the fine dust, regulations on PM generated from diesel cars are strengthened. There is a growing interest in diesel particulate filters (DPFs), a post-treatment device that removes exhaust gases from diesel vehicles. Therefore, one of the enhancements of the DPF efficiency is to reduce the pressure drop in the DPF, thereby increasing the efficiency of the filter and regeneration. In this study, the effect of cell density, channel shape, wall thickness, and inlet channel ratio of 5.66" SiC and Cordierite DPF on the pressure drop in DPF was investigated using ANSYS FLUENT simulator. As a result of the experiment, the pressure drop was smaller at 300 CPSI than 200 CPSI, and the anisotropy and O / S cell showed less than Isotropy by pressure drop of about 1,000 Pa. As the porosity increased by 10% the pressure drop was reduced by about 300 Pa and as the wall thickness increased by 0.05 mm, the pressure drop was increased by about 500 Pa.

Analysis on I-V of DGMOSFET for Device Parameters (소자파라미터에 대한 DGMOSFET의 전류-전압 분석)

  • Han, Ji-Hyung;Jung, Hak-Kee;Jeong, Dong-Soo;Lee, Jong-In
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.709-712
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    • 2012
  • In this paper, current-voltage have been considered for DGMOSFET, using the analytical model. The Possion equation is used to analytical. Threshold voltage is defined as top gate voltage when drain current is $10^{-7}A$. Investigated current-voltage characteristics of channel length changed length of channel from 20nm to 100nm. Also, The changes of current-voltage have been investigated for various channel thickness and doping concentration using this model, given that these parameters are very important in design of DGMOSFET. The deviation of conduction path and the influence of conduction path on current-voltage have been considered according to the dimensional parameters of DGMOSFET.

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The Characteristics of LLLC in Ultra Thin Silicon Oxides (실리콘 산화막에서 저레벨누설전류 특성)

  • Kang, C.S.
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.285-291
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    • 2013
  • In this paper, MOS-Capacitor and MOSFET devices with a Low Level Leakage Current of oxide thickness, channel width and length respectively were to investigate the reliability characterizations mechanism of ultra thin gate oxide films. These stress induced leakage current means leakage current caused by stress voltage. The low level leakage current in stress and transient current of thin silicon oxide films during and after low voltage has been studied from strss bias condition respectively. The stress channel currents through an oxide measured during application of constant gate voltage and the transient channel currents through the oxide measured after application of constant gate voltage. The study have been the determination of the physical processes taking place in the oxides during the low level leakage current in stress and transient current by stress bias and the use of the knowledge of the physical processes for driving operation reliability.

Analysis of subthreshold region transport characteristics according to channel doping for DGMOSFET using MicroTec (MicroTec을 이용한 DGMOSFET의 채널도핑에 따른 문턱전압이하영역 특성분석)

  • Han, Ji-Hyung;Jung, Hak-Kee;Lee, Jong-In;Jeong, Dong-Soo;Kwon, Oh-Shin
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.10a
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    • pp.715-717
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    • 2010
  • In this paper, the subthreshold characteristics have been alanyzed using MicroTec4.0 for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing since it can reduce the short channel effects due to structural characteristics. We have presented the short channel effects such as subthreshold swing and threshold voltage for DGMOSFET, using MicroTec, semiconductor simulator. We have analyzed for channel length, thickness and width to consider the structural characteristics for DGMOSFET. The subthreshold swing and threshold voltage have been analyzed for DGMOSFET using MicroTec since MicroTec is well verified as comparing with results of the numerical three dimensional models.

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An Analytical DC Model for HEMT's (헴트 소자의 해석적 직류 모델)

  • Kim, Young-Min
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.6
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    • pp.38-47
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    • 1989
  • A purely analytical model for HEMT's based on a two dimensional charge control simul-ation[4] is proposed. In this model proper treatment of diffusion effect of electron transport along a 2-DEG (two dimensional electron gas) channel is perfoemed. This diffusion effect is shown to effectively increase the bulk mibility and threshold voltage of the I-V curves compared to the existing models. The channel thickness and gate capacitance are expressed as functions of gate voltages covering subthreshold characteristics of HEMT's analytically. By introducing the finite channel opening and an effiective channel-length modulation, the solpe of the saturation region of the I-V curves ws modeled. The smooth transition of the I-V curves at linear-to-saturation regions of the I-V curves was possible using the continuous Troffimenkoff-type of field dependent mobility. Furthermore, a correction factor f was introduced to account for the finite transition section forming between a GCA and a saturated section. This factor removes large discrepancies in the saturation region of the I-V curve predicted by existing l-dimensional models.

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An Experimental Study on Flow Boiling Heat Transfer within Horizontal Rectangular Channels with Small Heights (미세 수평 사각 유로에서의 비등 열전달에 대한 실험적 연구)

  • Lee, Sang-Yong;Lee, Han-Ju
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.25 no.9
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    • pp.1209-1218
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    • 2001
  • The present paper proposes a new correlation for the flow boiling heat transfer coefficients in the low flow rate condition (Re(sub)LF$\leq$200) within horizontal rectangular channels with small gaps (heights). The gap between the upper and the lower plates of each channel ranges from 0.4 to 2mm while the channel width being fixed to 20mm. Refrigerant 113 was used as the test fluid. The mass flux ranges from 50 to 200kg/㎡s and the channel walls were uniformly heated with the heat flux range of 3-15kW/㎡. The quality range covers from 0.19 to 0.76 and the flow pattern is considered to be annular. The measured heat transfer coefficients increase with the mass flux and the local quality; however the effect of the heat flux appears to be minor. At the low mass flux condition, which is more likely with the smaller gap size, the heat transfer is primarily controlled by the liquid film thickness. The proposed F factor for the heat transfer coefficient in the range of Re(sub)LF$\leq$200 well represents the experimental data within the deviation of $\pm$20%. The Kandlikars flow boiling correlation covers the higher flow-rate range(Re(sub)LF>200) within the deviation of $\pm$20%.

Analysis of Subthreshold Characteristics for Double Gate MOSFET using Impact Factor based on Scaling Theory (스켈링이론에 가중치를 적용한 DGMOSFET의 문턱전압이하 특성 분석)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.9
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    • pp.2015-2020
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    • 2012
  • The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.

Analysis of On-Off Voltage △Von-off in Sub-10 nm Junctionless Cylindrical Surrounding Gate MOSFET (10 nm 이하 무접합 원통형 MOSFET의 온-오프전압△Von-off에 대한 분석)

  • Jung, Hak-kee
    • Journal of IKEEE
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    • v.23 no.1
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    • pp.29-34
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    • 2019
  • We investigated on-off voltage ${\Delta}V_{on-off}$ of sub-10 nm JLCSG (Junctionless Cylindrical Surrounding Gate) MOSFET. The gate voltage was defined as ON voltage for the subthreshold current of $10^{-7}A$ and OFF voltage for the subthreshold current of $10^{-12}A$, and the difference between ON and OFF voltage was obtained. Since the tunneling current was not negligible at 10 nm or less, we observe the change of ${\Delta}V_{on-off}$ depending on the presence or absence of the tunneling current. For this purpose, the potential distribution in the channel was calculated using the Poisson equation and the tunneling current was calculated using the WKB approximation. As a result, it was found that ${\Delta}V_{on-off}$ was increased due to the tunneling current in JLCSG MOSFETs below 10 nm. Especially, it increased rapidly with channel lengths less than 8 nm and increased with increasing channel radius and oxide thickness.