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Threshold and Flat Band Voltage Modeling and Device design Guideline in Nanowire Junctionless Transistors  

Kim, Jin-Young (Dept. of Electronics Engineering, University of Incheon)
Yu, Chong-Gun (Dept. of Electronics Engineering, University of Incheon)
Park, Jong-Tae (Dept. of Electronics Engineering, University of Incheon)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.12, 2011 , pp. 1-7 More about this Journal
Abstract
In this work, an analytical models for the threshold voltage and flat band voltage have been suggested and proved using 3-dimensional device simulator. The method for device design guideline and its example in nanowire junctionless transistor and example of device design of was also presented. One can find that the suggested model for threshold voltage and flat band voltage agrees with 3-dimension simulation results. The threshold voltage and flat band voltage are decreased with the increase of nanowire radius, gate oxide thickness, and channel impurity doping concentration. When the work function of gate material and the ratio of ON and OFF current is given, the device design guide line for nanowire junctionless transistor has been proposed. It is known that the device with high impurity channel concentration can be fabricated with th decreased of nanowire radius and gate oxide thickness.
Keywords
Silicon nanowire; Junctionless transistor; Threshold voltage; Flat band voltage;
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1 J. P. Colinge, C. W. Lee, A. Afzalian, N. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junction," Nature Nanotechnology, vol. 5, no. 3, pp. 225-229, 2010.   DOI   ScienceOn
2 C. W. Lee, A. N. Nazarov, I. Ferain, N. Dehdashti, R. Yan, P. Razavi, R. Yu, Rodrigo T. Doria, J. P. Colinge, "Low subthreshold slope in junctionless multiplegate transistors," Appl. Phys. Lett. vol. 96, pp. 102106, 2010.   DOI   ScienceOn
3 J. P. Raskin, J. P. Colinge, I. Ferain, A. Kranti, C. W. Lee, N. Dehdashti, R. Yan, P. razavi, R. Yu, "Mobility improvement in nanowire junctionless transistors by uniaxial strain," Appl. Phys. lett., vol. 97, pp. 042114, 2010.   DOI   ScienceOn
4 C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, J. P. Colinge, "Performance estimation of junctionless multiple gate transistors," Solid-state Electronics, vol. 54, no. 2, pp. 97-103, 2010.   DOI   ScienceOn
5 R. D. Trevisoli, M. A. Pavanello, R. T. Doria, M. de Souza, C. W. Lee, I ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. Kranti, and J. P. Colinge, "Analytical model for the threshold voltage of junctionless nanowire transistors," Proceeding of EUROSOI Workshop pp. 67-68, 2011.
6 N. lifshitz, "Dependence of the work-function difference between the polysilicon gate and silicon substrate on the doping level in polysilicon," IEEE Trans Electron Devices vol. 325, no. 3, pp. 617-621, 1985.
7 Jong Tae Park, and J. P. Colinge, "Multiple gate SOI MOSFETs :Device design guidelines," IEEE Trans. Electron Device, vol. 49, no,12, pp. 2222-2228, 2002.   DOI   ScienceOn
8 J. P. Colinge, "Multiple-gate SOI MOSFETs," Solid-state Electronics, vol.48, no.6, pp.897-905, 2004.   DOI   ScienceOn
9 R. Yan, D. Lynch, T. Cayron, D. Lederer, A Afzalian, C. W. Lee, and J. P. Colinge, "Sensitivity of trigate MOSFETs to random dopant incuced threshold voltage fluctuations," Solid-state Electronics, vol. 52, no.12, pp. 1872-1876, 2008.   DOI   ScienceOn
10 D. J. frank, R. H. Dennard, E. Novak, P. M. Solomon, Y. Taur, and H. S. P. Wong, "Device scaling limits of Si MOSFET and their application dependence," Proc. IEEE, vol. 89, no. 3, pp. 259-288, 2001.   DOI   ScienceOn
11 S. H. Jain, "Low resistance, low leakage ultrashallow $p^+$ junction formation using millisecond flash anneals," IEEE Trans Electron Devices, vol. 52, no. 7, pp. 1610-1615, 2003.
12 N. J. Quitoriano, and T. I. Kamins, "Integratable nanowire transistors," Nano letters, vol. 8, no. 12, pp. 4410-4414, 2008.   DOI   ScienceOn
13 P. Yang, R. Yan, and M. Fardy, "Semiconductor nanowire: what's next?," Nano Letters, vol. 11, no. 10, pp. 1529-1536, 2010.
14 M. Masahara, K .Endo, Y. Liu, T. Matsukawa, S. Ouchi, K. Ishii, E. Sugimata, E. Suzuki, "Demostration and analysis of accumulation-mode double-gate metal oxide semiconductor field effect transistor," Jpn J. Appl. Phys., vol. 45, no. 4b, pp. 079-3083, 2006.   DOI