• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.12
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• pp.2939-2945
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.755-758
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• 2014

This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend very differs with bottom gate voltage, channel length and thickness, and doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.903-908
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• 2015

This paper has analyzed threshold voltage shift for doping profile of asymmetric double gate(DG) MOSFET. Ion implantation is usually used in process of doping for semiconductor device and doping profile becomes Gaussian distribution. Gaussian distribution function is changed for projected range and standard projected deviation, and influenced on transport characteristics. Therefore, doping profile in channel of asymmetric DGMOSFET is affected in threshold voltage. Threshold voltage is minimum gate voltage to operate transistor, and defined as top gate voltage when drain current is $0.1{\mu}A$ per unit width. The analytical potential distribution of series form is derived from Poisson's equation to obtain threshold voltage. As a result, threshold voltage is greatly changed by doping profile in high doping range, and the shift of threshold voltage due to projected range and standard projected deviation significantly appears for bottom gate voltage in the region of high doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.713-716
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• 2013

The device performances of N-channel Tunneling FET have been characterized with different intrinsic length between drain and gate($L_{in}$), drain and source doping, permittivity and oxide thickness when the total effective channel length is constant. N-channel Tunneling FET of SOI structure have been used in characterization. $L_{in}$ was from 30nm to 70nm, dose concentration of drain and source were from $2{\times}10^{12}cm^{-2}$ to $2{\times}10^{15}cm^{-2}$ and from $1{\times}10^{14}cm^{-2}$ to $3{\times}10^{15}cm^{-2}$, permittivity was from 3.9 to 29, and oxide thickness was from 3nm to 9nm. The device performances were characterized by Subthreshold slope(S-slope), On/off ratio, and leakage current. From the simulation results, the leakage current have been reduced for long $L_{in}$ and low drain doping. S-slope have been reduced for high source doping, high permittivity and thin oxide thickness. With considering the leakage current and S-slope, it is desirable that are long $L_{in}$, low drain doping, high source doping, high permittivity and thin oxide thickness to optimize device performance in n-channel Tunneling FET.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.31-35
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• 2020

This study demonstrates metal-oxide based memtransistor device and the gate tunable memristive characteristic using atomic layer deposition (ALD) and ZnO n-type oxide semiconductor. We fabricated a memtransistor device having channel width 70 ㎛, channel length 5 ㎛, back gate, using 40 nm thick ZnO thin film, and measured gate-tunable memristive characteristics at each gate voltage (50V, 30V, 10V, 0V, -10V, -30V, -50V) under humidity of 40%, 50%, 60%, and 70% respectively, in order to investigate the relation between a memristive characteristic and hydrogen doping effect on the ZnO memtransistor device. The electron mobility and gate controllability of memtransistor device decreased with an increase of humidity due to increased electron carrier concentration by hydrogen doping effect. The gate-tunable memristive characteristic was observed under humidity of 60% 70%. Resistive switching ratio increased with an increase of humidity while it loses gate controllability. Consequently, we could obtain both gate controllability and the large resistive switching ratio under humidity of 60%.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.7-11
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• 2017

In this paper, we have studied the characteristics of NAND Flash memory in SONOS Poly-Si Thin Film Transistor (Poly-Si TFT) device. Source/drain junctions(S/D) of cells were not implanted and selective transistors were located in the end of cells. We found the optimum conditions of process by means of the estimation for the doping concentration of channel and source/drain of selective transistor. As the doping concentration was increased, the channel current was increased and the characteristic of erase was improved. It was believed that the improvement of erase characteristic was probably due to the higher channel potential induced by GIDL current at the abrupt junction. In the condition of process optimum, program windows of threshold voltages were about 2.5V after writing and erasing. In addition, it was obtained that the swing value of poly Si TFT and the reliability by bake were enhanced by increasing process temperature of tunnel oxide.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1373-1379
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• 1988

This paper describes a two-dimensional analysis of the potential distribution and electron concentration of the MODFET at channel using FDM. More exact analysis can be obtained by two-dimensional analysis which considers parasitic effects ignored in one-dimensional analysis. Using Poisson and Shrodinger equations, the potential distribution and the wave function are calculated within a constant error bound. As a result, the relations between the thickness of spacer, doping concentration of (n) AlGaAs layer, and the sheet density of the 2DEG (2 Dimensional Electron Gas) of MODFET at channel are suggested quantitively. The sheet density of the 2DEG is increased as the thickness of the spacer is decreased of the doping concentration of the (n)AlGaAs layer is lowered.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1815-1821
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• 2006

In this paper, the subthreshold swing has been analyzed for FinFET under channel length of 20nm. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current and WKB(Wentzel-Kramers-Brillouin) approximation to tunneling current. The cutoff current is obtained by simple adding two currents since two current is independent. The subthreshold swings by this model are compared with those by two dimensional simulation and two values agree well. Since the tunneling current increases especially under channel length of 10nm, the characteristics of subthreshold swing is degraded. The channel and gate oxide thickness have to be fabricated as am as possible to decrease this short channel effects, and this process has to be developed. The subthreshold swings as a function of channel doping concentrations are obtained. Note that subthreshold swings are resultly constant at low doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.789-794
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• 2017

Subthreshold current model is presented using analytical potential distribution of junctionless cylindrical surrounding-gate (CSG) MOSFET and threshold voltage shift is analyzed by this model. Junctionless CSG MOSFET is significantly outstanding for controllability of gate to carrier flow due to channel surrounded by gate. Poisson's equation is solved using parabolic potential distribution, and subthreshold current model is suggested by center potential distribution derived. Threshold voltage is defined as gate voltage corresponding to subthreshold current of $0.1{\mu}A$, and compared with result of two dimensional simulation. Since results between this model and 2D simulation are good agreement, threshold voltage shift is investigated for channel dimension and doping concentration of junctionless CSG MOSFET. As a result, threshold voltage shift increases for large channel radius and oxide thickness. It is resultingly shown that threshold voltage increases for the large difference of doping concentrations between source/drain and channel.

• Journal of IKEEE
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• v.27 no.4
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• pp.630-635
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• 2023

SiC is replacing the position of silicon in the power semiconductor field due to its superior resistance to adverse conditions such as high temperature and high voltage compared to silicon, which occupies the majority of existing industrial fields. In this paper, the gate of 4H-SiC Planar MOSFET, one of the power semiconductor devices, was formed with aluminium to make the contrast and parameter values consistent with polycrystalline Si gate, and the threshold voltage, breakdown voltage, and IV characteristics were studied by varying the channel doping concentration of SiC MOSFET.