• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.380-382
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• 2016

The mechanism for instability under PBS (positive bias stress) in amorphous SIZO (Si-In-Zn-O) thin-film transistors was investigated by analyzing the charge trapping mechanism. It was found that the bulk traps in the SIZO channel layer and the channel/dielectric interfacial traps are not created during the PBS duration. This result suggests that charge trapping in gate dielectric, and/or in oxide semiconductor bulk, and/or at the channel/dielectric interface is a more dominant mechanism than the creation of defects in the SIZO-TFTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.13-16
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• 1998

An anomalous current characteristics which show the superposition of a low current level and high current level at the subthreshold region when SONOSFETs are in memory states were investigated. We have assumed this phenomena were resulted from the effect of parasitic transistors by LOCOS isolation and were modeled to a parallel equivalent circuit of one memory transistor and two parasitic transistors. Theoretical curves are well fitted in measured log I$_{D}$-V$_{G}$ curves independent of channel width of memory devices. The difference between low current level and high current level is apparently decreased with decrease of channel width of devices because parasitic devices dominantly contribute to the current conduction with decrease of channel width of memory devices. As a result, we concluded that the LOCOS isolation has to selectively adopt in the design of process for charge-trap type NVSM.VSM.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.793-799
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• 2006

In this paper, the gate leakage current is first calculated using the experimental method between gate and drain by opening source electrode. the gate to drain current has been obtained with ground source. The difference between two currents has been tested and proves that the electric field generated by channel charge effect against the image force lowering.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1033-1041
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• 1990

In this paper, under pinch-off conditions, the gate-drain breakdown voltage characteristics of GaAs Power MESFET's as a function of device parameters such as channel thickness, doping concentration, gate length etc. are analyzed. Using the Green's function, the gate ionic charge induced by the depleted channel ionic charge is calculated. The impact ionization integral by avalanche multiplication between gate and drain is used to investigate breakdown phenomena. Especially, the localized excess surface charge effect as well as the uniform surface charge effect on breakdown voltage is considered.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.33-33
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• 2009

Silicon nano-structures have great potential in bionic sensor applications. Atomic force microscopy (AFM) anodic oxidation have many advantages for the nanostructure fabrication, such as simple process in atmosphere at room temperature, compatibility with conventional Si process. In this work, we fabricated simple FET structures with channel width W~ 10nm (nanowire) and $1{\mu}m$ (nano-ribbon) on ~10, 20 and 100nm-thinned silicon-on-insulator (SOI) wafers in order to investigate the surface effect on the transport characteristics of nano-channel. For further quantitative analysis, we carried out the 2D numerical simulations to investigate the effect of channel surface states on the carrier distribution behavior inside the channel. The simulated 2D cross-sectional structures of fabricated devices had channel heights of H ~ 10, 20, and 100nm, widths of L ~ $1{\mu}m$ and 10nm respectively, where we simultaneously varied the channel surface charge density from $1{\times}10^{-9}$ to $1{\times}10^{-7}C/cm2$. It has been shown that the side-wall charge of nanowire channel mainly affect the I-V characteristics and this was confirmed by the 2D numerical simulations.

• Journal of Life Science
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• v.16 no.1
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• pp.37-43
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• 2006

Gap junction is an ion channel forming between adjacent cells. It also acts as a membrane channel like sodium or potassium channels in a single cell. The amino acid residues up to the $10^{th}$ position in the amino (N)-terminus of gap junction hemichannel affect gating polarity as well as current-voltage (I-V) relation. While wild-type Cx32 channel shows negative gating polarity and inwardly rectifying I-V relation, T8D channel in which threonine residue at $8^{th}$ position is replaced with negatively charged aspartate residue shows reverse gating polarity and linear I-V relation. It is still unclear whether these changes are resulted from the charge effect or the conformational change of the N-terminus. To clarify this issue, we made a mutant channel harboring cysteine residue at the $8^{th}$ position (T8C) and characterized its biophysical properties using substituted-cysteine accessibility method (SCAM). T8C channel shows negative gating polarity and inwardly rectifying I-V relation as wild-type channel does. This result indicates that the substitution of cysteine residue dose not perturb the original conformation of wild-type channel. To elucidate the charge effect two types of methaenthiosulfonate (MTS) reagents (negatively charged $MTSES^-$ and positively charged $MTSET^+$) were used. When $MTSES^-$ was applied, T8C channel behaved as T8D channel, showing positive gating polarity and linear I-V relation. This result indicates that the addition of a negative charge changes the biophysical properties of T8C channel. However, positively charged $MTSET^+$ maintained the main features of T8C channel as expected. It is likely that the addition of a charge by small MTS reagents does not distort the conformation of the N-terminus. Therefore, the opposite effects of $MTSES^-$ and $MTSETT^+$ on T8C channel suggest that the addition of a charge itself rather than the conformational change of the N-terminus changes gating polarity and I-V relation. Furthermore, the accessibility of MTS reagents to amino acid residues at the $8^{th}$ position supports the idea that the N-terminus of gap junction channel forms or lies in the aqueous pore.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.726-728
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• 2012

In this paper, the threshold voltage characteristics have been analyzed by varying the channel thicknesses of Double Gate MOSFET. The channel thickness, as well as determining the size of the device which hardly affects SCE(Short Channel Effects), therefore the channel thicknesses is a very important parameter in the IC(Integrated circuit) design. In this study, using series charge distribution to analyze the threshold voltage on the channel thickness. Consequently, the threshold voltage decreases with increasing a channel thickness.