1 |
H. A. R. Wegner, A. J. Lincoln, H. C. Pao, M. R. O'Connel, R. E. Oleksiak, and H. Lawrence, "The variable threshold transistor, a new electricallyalterable, non-destructive read-only storage device," in IEDM Tech. Dig., vol. 13, pp. 70, 1967.
|
2 |
P. C. Y. Chen, "Threshold-alterable Si-gate MOS devices," IEEE Trans. on Electron Devices, vol. 24, no. 5, pp. 584-586, May 1977.
DOI
ScienceOn
|
3 |
2012 iSuppli annual report.
|
4 |
M. White, "On the Go with SONOS," IEEE Circuits and Device Magazine, vol. 16, no. 4, pp. 22-31, Jul. 2000.
DOI
|
5 |
H. Tanaka et al., "Bit cost scalable technology with punch and plug process for ultra high density flash memory," in Proc. Symp. VLSI Technol., pp. 14-15, Jun. 2007.
|
6 |
J. Jang et al., "Vertical cell array using TCAT technology for ultra-high density NAND flash memory," in Proc. Symp. VLSI Technol., pp. 192-193, Jun. 2009.
|
7 |
H. Silva and S. Tiwari, "A nanoscale memory and transistor using backside trapping," IEEE Trans. on Nanotechnology, vol. 3, no. 2, pp. 264-269, Jun. 2004.
DOI
ScienceOn
|
8 |
W. Kwon and T. King Liu, "Compact NAND flash memory cell design utilizing backside charge storage," in IEEE Silicon Nanoelectronics Workshop, Jun. 2010.
|
9 |
C. H. Lee, J. Choi, Y. Park, C. Kang, B. Choi, H. Kim, H. Oh, and W. Lee, "Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure," in Proc. Symp. VLSI Technol., pp. 118-119, Jun. 2008.
|
10 |
J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Kluwer Academic Publishers, 1997.
|