• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.589-590
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• 2008

This paper describes an improved design of graphic memory for QVGA ($320{\times}240\;RGB$) - scale 262k-color LCD Driver IC. A distributor block is adopted to reduce graphic RAM area, which is accomplished with 1/8 data lines of the previous structure. In line-read operation, the drivabilty of memory array cell is improved by partitioning a word line according to the row address. The proposed graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and verified using Hsim.

• 전자공학회논문지C
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• 제35C권8호
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• pp.33-41
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• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.

• Journal of Power Electronics
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• 제16권2호
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• pp.532-541
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• 2016

A single-phase asymmetrical cascaded multilevel inverter is introduced with the goal of increasing power quality with the reduction of power in insulated-gate bipolar transistor (IGBT) switches. In the present work, the proposed inverter topology is analyzed and generalized with respect to different proposed algorithms for choosing different voltage source values. To prove the advantages of the proposed inverter, a case study involving a 17-level inverter is conducted. The simulation and experimental results with reduced THD are also presented and compared with the MATLAB/SIMULINK simulation results. Finally, the proposed topology is compared with different multilevel inverter topologies available in the literature in terms of the number of IGBT switches required with respect to the number of levels generated in the output of inverter topologies.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.921-923
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• 1999

비휘발성 메모리의 고집적화와 적응학습형 뉴럴 소자의 실현을 위하여 1-트랜지스터 구조 강유전체 비휘발성 메모리(MFS-FET)를 SOI 기판위에 제작하고 평가하였다. 먼저 SBT($Sr_{0.8}Bi_{2.2}Ta_{2}O_{9}$)를 직접 Si위에 증착하고 C-V를 측정하여 1V의 메모리 윈도우를 얻음으로써 비휘발성 메모리로써의 동작가능성을 확인하였다. 또한 다양하게 게이트의 W/L 비를 바꾸어서 MFS-FET를 제작하여 다양한 드레인 전압-드레인 전류 특성을 얻었고 실제로 쓰기와 읽기 동작을 수행하여 MFS-FET가 비휘발성 메모리로써 제대로 동작하고 있음을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.52-52
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• 2011

A novel deposition process for n-type nanocrystalline silicon (n-type nc-Si) thin films at room temperature has been developed by adopting the neutral beam assisted chemical vapor deposition (NBa-CVD). During formation of n-type nc-Si thin film by the NBa-CVD process with silicon reflector electrode at room temperature, the energetic particles could induce enhance doping efficiency and crystalline phase in polymorphous-Si thin films without additional heating on substrate; The dark conductivity and substrate temperature of P-doped polymorphous~nano crystalline silicon thin films increased with increasing the reflector bias. The NB energy heating substrate(but lower than $80^{\circ}C$ and increase doping efficiency. This low temperature processed doped nano-crystalline can address key problem in applications from flexible display backplane thin film transistor to flexible solar cell.

• ETRI Journal
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• 제28권2호
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• pp.175-181
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• 2006

A new CMOS voltage-controlled fully-differential transconductor is presented. The basic structure of the proposed transconductor is based on a four-MOS transistor cell operating in the triode or saturation region. It achieves a high linearity range of ${\pm}\;1\;V$ at a 1.5 V supply voltage. The proposed transconductor is used to realize a new fully-differential Gm-C low-pass filter with a minimum number of transconductors and grounded capacitors. PSpice simulation results for the transconductor circuit and its filter application indicating the linearity range and verifying the analytical results using $0.35\;{\mu}m$ technology are also given.

• ETRI Journal
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• 제32권3호
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• pp.406-413
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• 2010

In order to guarantee the proper operation of a recessed channel array transistor (RCAT) pseudo SRAM, the back-bias voltage must be changed in response to changes in temperature. Due to cell drivability and leakage current, the obtainable back-bias range also changes with temperature. This paper presents a pseudo SRAM for mobile applications with an adaptive back-bias voltage generator with a negative temperature dependency (NTD) using an NTD VBB detector. The proposed scheme is implemented using the Samsung 100 nm RCAT pseudo SRAM process technology. Experimental results show that the proposed VBB generator has a negative temperature dependency of -0.85 $mV/^{\circ}C$, and its static current consumption is found to be only 0.83 ${\mu}A$@2.0 V.

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.372-377
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• 2003

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35$\mu\textrm{m}$ CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34${\AA}$, nitride of 73${\AA}$ and blocking oxide of 34${\AA}$ . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.