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http://dx.doi.org/10.4218/etrij.10.0109.0366

Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM  

Son, Jong-Pil (Memory Division, Samsung Electronics Corporation)
Byun, Hyun-Geun (Department of Semiconductor, SSIT, Samsung Electronics Corporation)
Jun, Young-Hyun (Memory Division, Samsung Electronics Corporation)
Kim, Ki-Nam (Memory Division, Samsung Electronics Corporation)
Kim, Soo-Won (Department of Electronics Engineering, Korea University)
Publication Information
ETRI Journal / v.32, no.3, 2010 , pp. 406-413 More about this Journal
Abstract
In order to guarantee the proper operation of a recessed channel array transistor (RCAT) pseudo SRAM, the back-bias voltage must be changed in response to changes in temperature. Due to cell drivability and leakage current, the obtainable back-bias range also changes with temperature. This paper presents a pseudo SRAM for mobile applications with an adaptive back-bias voltage generator with a negative temperature dependency (NTD) using an NTD VBB detector. The proposed scheme is implemented using the Samsung 100 nm RCAT pseudo SRAM process technology. Experimental results show that the proposed VBB generator has a negative temperature dependency of -0.85 $mV/^{\circ}C$, and its static current consumption is found to be only 0.83 ${\mu}A$@2.0 V.
Keywords
Pseudo SRAM; memories; RCAT; temperature; back-bias voltage generator;
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1 S. Yoo et al., "Variable Vcc Design Techniques for Battery-Operated DRAM's," IEEE J. Solid-State Circuits, vol. 28, no. 4, Apr. 1993, pp. 499-503.   DOI   ScienceOn
2 R.J. Baker, CMOS Circuit Design, Layout, and Simulation, 2nd ed., IEEE Press, 2005.
3 T. Sakurai and A.R. Newton, "Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, Apr. 1990, pp. 584-594.   DOI   ScienceOn
4 I.M. Filanovsky and A. Allam, "Mutual Compensation of Mobility and Threshold Voltage Temperature Effects with Applications in CMOS Circuits," IEEE Trans. Circuits Syst. I, vol. 48, no. 7, Jul. 2001, pp. 876-884.   DOI   ScienceOn
5 Y. Tsukikawa et al., "An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAMs," IEEE J. Solid-State Circuits, vol. 29, Apr. 1994, pp. 534-538.   DOI   ScienceOn
6 K.S. Min, "Efficient Back-Bias Voltage Generator with Suppressed Parasitic Bipolar Action for Low-Voltage DRAMs," Electron. Lett. vol. 37, no. 1, Jan. 2001, pp. 6-8.   DOI   ScienceOn
7 Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998.
8 D.S. Min et al., "Temperature-Compensation Circuit Techniques for High-Density CMOS DRAM's," IEEE J. Solid-State Circuits, vol. 27, no. 4, Apr. 1992, pp. 626-631.   DOI   ScienceOn
9 Y.P. Kim et al., "Junction Leakage Current Degradation Under the Off-State Bias-Temperature Stress: A New Reliability Assessment Method for High-Density DRAMs," IEEE Trans. Device and Materials Reliability, vol. 1, Jun. 2001, pp. 104-108.   DOI   ScienceOn
10 C.C. Wang, Y.L. Tseng, and C.C. Chiu, "A Temperature-Insensitive Self-Recharging Circuitry Used in DRAMs," IEEE Trans. VLSI Syst., vol. 13, Mar. 2005, pp. 405-408.   DOI
11 W.L. Martino et al., "An On-Chip Back-Bias Generator for MOS Dynamic memory," IEEE J. Solid-State Circuits, vol. 15, no. 5, Oct. 1980, pp. 820-826.   DOI   ScienceOn
12 J.Y. Kim et al., "The Breakthrough in Data Retention Time of DRAM Using Recess-Channel-Array Transistor (RCAT) for 88 nm Feature Size and Beyond," Proc. Symp. VLSI Technol., Dig. Tech. Papers, 2003, pp. 11-12.
13 W.S. Lee et al., "Analysis on Data Retention Time of Nano-Scale DRAM and Its Prediction by Indirectly Probing the Tail Cell Leakage Current," IEDM Tech. Dig., 2004, pp. 395-398.