• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.269-274
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• 2004

Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3 ${\mu}A$ with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.7-7
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• 2009

In this paper, we investigated the dependence of HCI (Hot Carrier Immunity) degradation and device performance on channel orientation in sub-micron PMOSFET. Although device performance ($I_{D.sat}$ vs. $I_{Off}$) was improved as the transistor angle increased HC immunity was degraded. Therefore, consideration of reliability characteristics as well as dc device performance is highly necessary in channel stress engineering of next generation CMOSFETs.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.97-106
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• 1992

In integrated circuits, protection circuits are required to protect the internal nodes from the harmful ESD(Electrostatic discharge). This paper discusses the characteristics of the circuit components in ESD protection circuitry in order to analyze the ESD phenomina, and the design methodalogy of ESD protection circuits, using test pattern with a variation of the number of diode and transistor. The test devices are fabricated using a 0.8$\mu$m CMOS process. SPICE simulation was also carried out to relate output node voltage and measured ESD voltage. With increasing number of diodes and transistors in protection circuit, the ESD voltage also increases. The ESD voltage of the bi-directional circuit for both input and output was 100-300[V], which in higher than that of only output(uni-directional) circuit. In addition, the ESD protection circuit with the diode under the pad region was useful for the reduction of chip size and parasitic resistance. In this case, ESD voltage was improved to a value about 400[V].

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04a
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.857-860
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• 1991

This paper describes a High-Speed 8-bit Current-Mode BiCMOS A/D Converter. The characteristics of this A/D Converter are as fellows. First, as ADC is operating in current-mode we can obtain the properties of increase of converting speed, low noise, and wideband. Second, the properties of high switching speed in bipolar transistor and of high packing density, low power consumption in MOS trnsistor are combined. Finally we reduce chip area by designing it with subranging mode and improve the converting speed by performing subtraction directly, which doesn't need D/A convertings, using current switching element. This converter is composed of two 4-bit ADC, current soure array which provides signal and reference current, current comparator and encoding network.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.1
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• pp.41-48
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• 1998

This paper proposes a new addition algorithm to improve the addition speed which is one of the important factors for data path functions. We have designed a fast 64-bit adder utilizing al dynamic chain architecture based on the proposed Sum-Selector Generation (SSG) algorithm. Proposed adder is designed with pass-transistor logicto achieve a high speed operation in low voltage circumstance. Realized 64-bit adder with 0.8.mu.m CMOS double-metal process technology has been fully tested. it operates at 185 MHz with 5.0V and chip area occupies 3.66mm$^{2}$. It is also demonstrated that designed adder operates even at 2.0V power supply condition.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.67-70
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• 2003

In this paper the main topologies of one-bit full adders, including the most interesting of those recently proposed, are analyzed and compared for speed, power consumption, and power-delay product. The comparison has been performed on circuits, optimized transistor dimension to minimize power-delay product. The investigation has been carried out with properly defined simulation runs on a Cadence environment using a 0.25-${\mu}m$ process, also including the parasitics derived from layout. Performance has been also compared for different supply voltage values. Thus design guidelines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare n-bit adders implemented as a chain of one-bit full adders. The results differ from those previously published both for the more realistic simulations carried out and the more appropriate figure of merit used. They show that, except for short chains of blocks or for cases where minimum power consumption is desired, topologies with only pass transistors or transmission gates are not attractive.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.304-307
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• 2013

Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies, and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by $CF_4$ plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result, we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.523-526
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• 2001

In this paper, we design and fabricate the high-efficiency and low-power switched-capacitor DC-DC converter. This converter consists of internal oscillator, output driver and output switches. The internal oscillator has 100kHz oscillation frequency and the output switches composed of one pMOS transistor and three nMOS transistors. According to the configuration of two external capacitors, the converter has three functions that are the Inverter, Doubler and Divider. The proposed converter is fabricated through the 0.8$\mu\textrm{m}$ 2-poly, 2-metal CMOS process. The simulation and experimental result for fabricated IC show that the proposed converter has the voltage conversion efficiency of 98% and power efficiency more than 95%.

• ETRI Journal
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• v.26 no.4
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• pp.307-314
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• 2004

The application of a discrete pseudomorphic high electron mobility transistor (p-HEMT) as a grounded switch allows for the development of low cost phase shifters and phase modulators operating in a Ku band. This fills the gap in the development of phase control devices comprising p-i-n diodes and microwave monolithic integrated circuits (MMICs). This paper describes a discrete p-HEMT characterization and modeling in switching mode as well as the development of a low-cost four-bit phase shifter and direct quadrature phase shift keying (QPSK) modulator. The developed devices operate in a Ku band with parameters comparable to commercially available MMIC counterparts. Both of them are CMOS compatible and have no power consumption. The parameters of the QPSK modulator are very close to the requirements of available standards for satellite earth stations.