• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.5
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• pp.678-681
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• 2020

In this paper, we analyzed the noise figure of cascode low noise amplifier (LNA) based on the measured data of 65nm CMOS devices. By using the channel thermal noise model of transistors, we expanded noise figure equation and divided the equation into three parts to see its contributions to noise figure. We also varied design parameters such as bias point, transistor gate width, and operating frequency. Our results show that different noise sources dominate at the different operating frequencies. One can easily find the noise transition frequency with device models in ahead of the practical design. Therefore, this research provides a low noise design approach for different operating frequencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.82-88
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• 2020

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.289-294
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• 2008

A 77 GHz 3-stage low noise amplifier (LNA) employing one common source and two cascode stages is developed using $0.13{\mu}m$ CMOS process. To compensate for the low gain which is caused by lossy silicon substrate and parasitic element of CMOS transistor, positive feedback technique using parasitic inductance of bypass capacitor is adopted to cascode stages. The developed LNA shows gain of 7.2 dB, Sl1 of -16.5 dB and S22 of -19.8 dB at 77 GHz. The return loss bandwidth of LNA is 71.6 to 80.9 GHz (12%). The die size is as small as $0.7mm\times0.8mm$ by using bias line as inter-stage matching networks. This LNA shows possibility of 77 GHz automotive RADAR system using $0.13{\mu}m$ CMOS process, which has advantage in cost compared to sub-100 nm CMOS process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.140-144
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• 2004

The selectable dual band LNA usually uses common source transistor pair each input of which is selectively driven at a different frequency in a series resonant form. This paper analyzes the degradation in noise figures of the MOSFET common source pair with series resonance when it is driven concurrently at both inputs with different frequencies as a concurrent dual band LNA. Results of analysis will be compared with the measured noise figures of CMOS LNA with double inputs fabricated in 0.18 $\mu\textrm{m}$ CMOS process. Additionally, analyzing the contributions of FET channel noise and source noise from the LNA operating in the other band, this paper proposes optimum matching topology which minimizes the added noises for concurrent operation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1222-1228
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• 2010

This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a $0.5{\mu}m$ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.3 s.357
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• pp.78-84
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• 2007

A multistandard direct-conversion mixer for WCDMA, Wibro, and 802.11a/b/g is designed in 0.18 um CMOS technology To support multistandard and to reduce the chip area the switched inductor is used as the matching method. This switched inductor matching network selects the mixer's operation frequency band by turning on or off the switch transistor. Since the performances of mixer and operation frequency can be affected by the parasitic of switch transistor the mixer should be designed with the optimized size of switch to minimize parasitic effects. Proposed mixer is able to achieve return loss less than -13 dB in $2.1\sim2.5GHz$ and $5.1\sim5.9GHz$ bands with the suitable performance to meet requirements of WCDMA, WiBro, and 802.11a/b/g.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.239-244
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• 2013

This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a $1{\mu}m$ high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.88-92
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• 2010

Bottom gate and top gate field-effect transistor based carbon nanotube(CNT) were fabricated by CMOS process. Carbon nanotube directly grown by thermal chemical vapor deposition(CVD) using Ethylene ($C_2H_4$) gas at $700^{\circ}C$. The growth properties of CNTs on the device were analyzed by SEM and AFM. The electrical transport characteristics of CNT FET were investigated by I-V measurement. Transport through the nanotubes is dominated by holes at room temperature. By varying the gate voltage, bottom gate and top gate field-effect transistor successfully modulated the conductance of FET device.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.251-254
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• 1999

In this paper V-I(Voltage to Current) converter using the series composite transistor is presented. Due to the series composite transistor employs operating in the saturation region and triode region, the proposed circuit has wide input range at low voltage. The designed V-I converter has simulated by HSPICE using 0.6${\mu}{\textrm}{m}$ n-well CMOS process with a $\pm$2.5V supply voltage. Simulation results show that the THD can be 0.81% at 4 $V_{p-p}$ differential input voltage when frequency of input signal is 10MHz.z.