Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Implementation of Low Power MAC using Improvement of Multiply/Subtract Operation Method and PTL Circuit Design Methodology

승/감산 연산방법의 개선 및 PTL회로설계 기법을 이용한 저전력 MAC의 구현

  • Sim, Gi-Hak (Dept.of Electronics Engineering Chung Buk, National University) ;
  • O, Ik-Gyun (Dept.of Electronics Engineering Chung Buk, National University) ;
  • Hong, Sang-Min (Dept.of Electronics Engineering Chung Buk, National University) ;
  • Yu, Beom-Seon (Dept.of Electronics Engineering Chung Buk, National University) ;
  • Lee, Gi-Yeong (Dept.of Electronics Engineering Chung Buk, National University) ;
  • Jo, Tae-Won (Dept.of Electronics Engineering Chung Buk, National University)
  • 심기학 (충북대학교 전자공학과) ;
  • 오익균 (충북대학교 전자공학과) ;
  • 홍상민 (충북대학교 전자공학과) ;
  • 유범선 (충북대학교 전자공학과) ;
  • 이기영 (충북대학교 전자공학과) ;
  • 조태원 (충북대학교 전자공학과)
  • Published : 2000.04.01
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Abstract

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

시스템 설계의 각 단계에서 저전력 설계기법을 적용하여 8×8＋20비트의 MAC을 설계하였다. 알고리듬레벨에서는 MAC의 중요한 명령어 중의 하나인 승/감산연산을 위한 하드웨어의 설계에서 기존의 방식에 비하여 트랜지스터를 감소할 수 있는 새로운 기법을 제안하였으며, 회로 레벨에서는 동일한 로직을 CMOS로 구현한 경우보다 PDP(power-delay-product) 측면에서 우수한 성능을 가지는 NMOS pass-transistor 로직으로 구성된 새로운 Booth 셀렉터 회로를 제안하였다. 구조 레벨에서 최종단 덧셈기는 전력소모, 동작속도, 면적, 설계 규칙성 측면에서 가장 우수한 ELM 덧셈기를 사용하였고, 레지스터는 비트당 트랜지스터의 수가 적은 동적 CMOS 단일모서리 천이 플립플롭을 적용하였다. 동작속도를 높이기 위한 방법으로는 2단 파이프라인 구조를 적용했으며, Wallace 트리 블록에 고속 4：2 압축기를 이용하였다. 0.6㎛ 단일폴리, 삼중금속 CMOS 공정으로 설계된 MAC은 모의실험 결과 곱셈 연산시 최대 200㎒ 3.3V에서 35㎽의 전력을 소모하였고, MAC 연산시 최대 100㎒에서 29㎽의 전력을 소모하였다.

Keywords

References

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