• Title/Summary/Keyword: CMOS VLSI

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A study on DTCNN hardware implementation for image processing (영상처리를 위한 DTCNN 하드웨어 구현에 관한 연구)

  • 문성용
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.4
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    • pp.96-104
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    • 1998
  • In this paper, the circuit of DTCNN designed using dilation and erosion operation, a basic operation of gray-scale morphology, also each cell designed PE in order to having extension using the local connectivity. In this PE design, connection of between cell and cell become simple. And it is realized to easily VLSI realization as well as to circuit to be parallel processing. As the resutls of simulations, the proposed method was verified to improved more operation speed than the sequential data processing, parallel processing DTCNN was implemented in a 0.8.mu.m CMOS technology using COMPASS Tool.

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Building Blocks for Current-Mode Implementation of VLSI Fuzzy Microcontrollers

  • Huerats, J.L.;Sanchez-Solano, S.;Baturone, I.;Barriga, A.
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1993.06a
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    • pp.929-932
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    • 1993
  • A fuzzy microcontroller is presented implementing a simplified inference mechanism. Fuzzification, rule composition and defuzzification are carried out by means of (basically) analog current-mode CMOS circuits operating in strong inversion. Also a voltage interface is provided with the external world. Combining analog and digital techniques allow a programming capability.

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Design of a High Performance 32$\times$32-bit Multiplier Based on Novel Compound Mode Logic and Sign Select Booth Encoder (새로운 복합모드로직과 사인선택 Booth 인코더를 이용한 고성능 32$\times$32-bit 곱셈기의 설계)

  • Kim, Jin-Hwa;Song, Min-Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.3
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    • pp.205-210
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    • 2001
  • In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

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Pipelined Wake-Up Scheme to Reduce Power-Line Noise of MTCMOS Megablock Shutdown for Low-Power VLSI Systems (저전력 VLSI 시스템에서 MTCMOS 블록 전원 차단 시의 전원신 잡음을 줄인 파이프라인 전원 복귀 기법)

  • 이성주;연규성;전치훈;장용주;조지연;위재경
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.77-83
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    • 2004
  • In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.

The ASIC Design of the Adaptive De-interlacing Algorithm with Improved Horizontal and Vertical Edges (알고리즘을 적용한 ASIC 설계)

  • Han, Byung-Hyeok;Park, Sang-Bong;Jin, Hyun-Jun;Park, Nho-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.7
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    • pp.89-96
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    • 2002
  • In this paper, the ADI(Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and the architecture designed through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using $0.6{\mu}m$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

A Low Power SRAM Using Elevated Source Level Memory Cells (소스 전압을 높인 메모리 셀을 이용한 저전력 SRAM)

  • 양병도;김이섭
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.93-98
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    • 2004
  • A low power SRAM using elevated source level memory cells is proposed to save the write power of SRAM. It reduces the swing voltages of the bit lines and data bus by elevating the source level of the memory cells from GND to $V_{T}$ and lowering the precharge level of the bit lines and data bus from $V_{DD}$ to $V_{DD}$ - $V_{T}$. It saves the write power of SRAM without area overhead and speed degradation. An SRAM with 8K${\times}$32bits is fabricated in a 0.25um CMOS process. It saves 45% of the power in write cycles at 300MHz with 2.5V. The maximum operating frequency is 330MHz.

Design of a Capacitive Detection Circuit using MUX and DLC based on a vMOS (vMOS 기반의 DLC와 MUX를 이용한 용량성 감지회로)

  • Jung, Seung-Min
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.11 no.4
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    • pp.63-69
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    • 2012
  • This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

Performance Analysis of 403.5MHz CMOS Ring Oscillator Implemented for Biomedical Implantable Device (생체 이식형 장치를 위해 구현된 403.5MHz CMOS 링 발진기의 성능 분석)

  • Ferdousi Arifa;Choi Goangseog
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.19 no.2
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    • pp.11-25
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    • 2023
  • With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.

An Efficient Soft-Output MIMO Signal Detection Method Based on Multiple Channel Ordering Technique and Its VLSI Implementation (다중 채널 순서화 기술 기반 효율적인 Soft-Output MIMO 신호검출 기법과 VLSI 구현)

  • Im, Tae-Ho;Yu, Sung-Wook;Kim, Jae-Kwon;Cho, Yong-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.12C
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    • pp.1044-1051
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    • 2010
  • In this paper, we propose an efficient soft-output signal detection method for spatially multiplexed multiple input multiple output (MIMO) systems. The proposed method is based on the ordered successive interference cancellation (OSIC) algorithm, but it significantly improves the performance of the original OSIC algorithm by solving the error propagation problem. The proposed method combines this enhanced OSIC (ESIC) algorithm with a multiple ordering technique in a very efficient way. As a result, the log likelihood ratio (LLR) values can be computed by using a very small set of candidate symbol vectors. The proposed method has been implemented with a $0.13{\mu}m$ CMOS technology for a $4{\times}4$ 16-QAM MIMO system. The simulation and implementation results show that the proposed detector provides a very good solution in terms of performance and hardware complexity.

A New ASIC Design of Digital Hologram Generation Circuit for 12×12 Block (12×12 블록의 디지털 홀로그램 생성 회로의 ASIC 설계)

  • Lee, Yoon-Hyuk;Kim, Dong-Wook;Seo, Young-Ho
    • Journal of Broadcast Engineering
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    • v.21 no.6
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    • pp.944-956
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    • 2016
  • In this paper, we propose a new hardware architecture to generate computer-generated holograms based on the block based calculation method and implement a VLSI (very large scaled integrated circuit) in ASIC (application specific integrated circuit) environment. The proposed hardware has a structure that can produce a part of a hologram in the unit of a block in parallel. After calculating a block of a hologram by using an object point, the calculation is repeated to all object points and intermediate results from them are accumulated to produce a final block of a hologram. Through this structure, we can make various size of holograms with the optimized memory access in real-time operation. The proposed hardware was implemented in the Hynix 0.18um CMOS technology of Magna chip Inc. and has 876,608 gate counts. It can generate complex holograms unlike the previous researches and stably operate in the clock frequency of 200MHz.