Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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The ASIC Design of the Adaptive De-interlacing Algorithm with Improved Horizontal and Vertical Edges

알고리즘을 적용한 ASIC 설계

  • Han, Byung-Hyeok (Dept. of Information & Telecommunication Eng. HOSEO Univ.) ;
  • Park, Sang-Bong (Dept. of Information & Telecommunication Eng. SEMYUNG Univ.) ;
  • Jin, Hyun-Jun (Dept. of Information & Telecommunication Eng. HOSEO Univ.) ;
  • Park, Nho-Kyung (Dept. of Information & Telecommunication Eng. HOSEO Univ.)
  • 한병혁 (湖西大學校 情報通信工學科) ;
  • 박상봉 (世明大學校 情報通信工學科) ;
  • 진현준 (湖西大學校 情報通信工學科) ;
  • 박노경 (湖西大學校 情報通信工學科)
  • Published : 2002.07.01
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Abstract

In this paper, the ADI(Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and the architecture designed through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using $0.6{\mu}m$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

본 논문은 ELA알고리듬의 수평방향 및 수직방향과 대각선 방향을 판단하여 수평 윤곽선 및 수직 윤곽선 특성을 시각적인 면과 객관적인 면에서 개선한 ADI(adaptive de-interlacing)알고리듬을 제안하고, 제안한 알고리듬에 대한 수직을 전개, 이를 C, Matlab을 이용하여 검증하였다. 제안한 알고리듬의 구조를 $0.6{\mu}m$ 2-poly 3-metal CMOS 표준 라이브러리를 적용하고 Cadence툴을 이용하여 회로 및 논리 시뮬레이션을 수행하고 레이아웃을 작성하였다.

Keywords

References

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