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http://dx.doi.org/10.12815/kits.2012.11.4.063

Design of a Capacitive Detection Circuit using MUX and DLC based on a vMOS  

Jung, Seung-Min (한신대학교 IT대학 정보통신학부)
Publication Information
The Journal of The Korea Institute of Intelligent Transport Systems / v.11, no.4, 2012 , pp. 63-69 More about this Journal
Abstract
This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.
Keywords
DLC; MUX; Capacitive sensing; Gray scale image; CMOS; VLSI;
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