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Pipelined Wake-Up Scheme to Reduce Power-Line Noise of MTCMOS Megablock Shutdown for Low-Power VLSI Systems  

이성주 (숭실대학교 정보통신전자공학부)
연규성 (숭실대학교 정보통신전자공학부)
전치훈 (숭실대학교 정보통신전자공학부)
장용주 (숭실대학교 정보통신전자공학부)
조지연 (숭실대학교 정보통신전자공학부)
위재경 (숭실대학교 정보통신전자공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.10, 2004 , pp. 77-83 More about this Journal
Abstract
In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.
Keywords
Megablock shutdown; wake-up; pilelined structure; MTCMOS; cut-off switch; leakage power;
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