[KSCI] Korea Science Citation Index Service

A Low Power SRAM Using Elevated Source Level Memory Cells

양병도 (KAIST 전자전산학과)
김이섭 (KAIST 전자전산학과)

Publication Information

Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.8, 2004 , pp. 93-98 More about this Journal

Abstract

A low power SRAM using elevated source level memory cells is proposed to save the write power of SRAM. It reduces the swing voltages of the bit lines and data bus by elevating the source level of the memory cells from GND to $V_{T}$ and lowering the precharge level of the bit lines and data bus from $V_{DD}$ to $V_{DD}$ - $V_{T}$ . It saves the write power of SRAM without area overhead and speed degradation. An SRAM with 8K ${\times}$ 32bits is fabricated in a 0.25um CMOS process. It saves 45% of the power in write cycles at 300MHz with 2.5V. The maximum operating frequency is 330MHz.

Keywords

VLSI; CMOS; SRAM; low power; and low swing;

Citations & Related Records

Reference

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4	S. Hattori and T. Sakurai, '90% Write Power Saving SRAM Using Sense-Amplifying Memory Cell,' Symp. on VLSI Circuits, pp. 46-47, 2002 DOI ScienceOn

KSCI

A Low Power SRAM Using Elevated Source Level Memory Cells 소스 전압을 높인 메모리 셀을 이용한 저전력 SRAM

A Low Power SRAM Using Elevated Source Level Memory Cells