• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.236-242
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• 2021

In this paper, we report the fabrication of the tip-on-gate of a field-effect-transistor (ToGoFET) probe using a standard complementary metal-oxide-semiconductor (CMOS) process and the performance evaluation of the fabricated probe. After the CMOS process, I-V characteristic measurement was performed on the reference MOSFET. We confirmed that the ToGoFET probe could be operated at a gate voltage of 0 V due to channel ion implantation. The transconductance at the operating point (Vg = 0 V, Vd = 2 V) was 360 ㎂/V. After the fabrication process was completed, calibration was performed using a pure metal sample. For sensitivity calibration, the relationship between the input voltage of the sample and the output current of the probe was determined and the result was consistent with the measurement result of the reference MOSFET. An oxide sample measurement was performed as an example of an application of the new ToGoFET probe. According to the measurement, the ToGoFET probe could spatially resolve a hundred nanometers with a height of a few nanometers in both the topographic image and the ToGoFET image.

• Journal of Radiation Industry
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• v.8 no.3
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• pp.147-153
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• 2014

This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a $2{\times}1$ butted CMOS image sensor module which except for the size of PCB is $170mm{\times}170mm$. And the pixel size is $55{\mu}m{\times}55{\mu}m$ and the number of pixels is $3,072{\times}3,072$. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.49-59
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• 2001

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the growing needs for lowcost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology so far, much of them have been developed in ETRI, and from them forecasts technology trends in the near future.

• Journal of Information Display
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• v.8 no.1
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• pp.1-5
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• 2007

We have developed a CMOS LTPS process which requires only five photolithographic masks and only one ion doping step. Drain/Source areas of NMOS TFTs were formed by PECVD deposition of a highly doped precursor layer while PMOS contact areas were defined by ion implantation. Single TFTs, inverters, ring oscillators and shift registers were fabricated. N and p-channel devices reached field effect mobilities of $173cm^2$/Vs and $47cm^2$/Vs, respectively.

• ETRI Journal
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• v.32 no.3
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• pp.457-459
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• 2010

A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.55-60
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• 1984

With the advancement of CMOS technology, it has become attractive to employ complex gate structures in realizing digital circuits. A new test generation algorithm for CMOS complex gates to detect all stuck-open and stuck-on faults considering internal gate response and unknown state is proposed. Minimal and complete set can be derived by this algorithm. Also, it is verified that such a test set is generated applying this algorithm to arbitrary CMOS complex gates by computer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.102-106
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• 2005

A low dark current CMOS image sensor (CIS) pixel without any process modification is developed. Dark current is mainly generated at the interface region of shallow trench isolation (STI) structure. Proposed pixel reduces the dark current effectively by separating the STI region from the photodiode junction using simple layout modification. Test sensor array that has both proposed and conventional pixels is fabricated using 0.18 m CMOS process and the characteristics of the sensor are measured. The result shows that the dark current of the proposed pixel is 0.93fA/pixel that is two times lower than the conventional design.

• Journal of the Optical Society of Korea
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• v.20 no.5
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• pp.623-627
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• 2016

A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10⁻⁹ bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.12
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• pp.125-130
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• 2004

The characteristics of on-chip spiral rectangular inductors in CMOS process are investigated through the simulation and experiment. The ADS-momentum is used for EM simulation, and the spiral inductors are fabricated with Hynix 0.35㎛ CMOS process. This research mainly concerned the effects of the geometric change in terms of the number of turns and the width of micro strip line. The measured and simulated results show that the Hynix 0.35㎛ process could support a top metal spiral inductor of 1nH to 6nH with Q-factor less than 5.