• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.10
• /
• pp.1107-1113
• /
• 2009

In this paper, the design and implementation of K-Band frequency dividers using 130 nm CMOS process are presented. A Miller frequency divider is presented, which realizes a division range from 20 to 25 GHz with 7.2 mW power consumption from 1.2 V supply. The layout size of the core circuit is about $315{\times}246\;um^2$. In addition, a CML frequency divider which divides the output signal of the Miller frequency divider is also presented, which realizes a division range from 8.5 to 13 GHz with 5.7 mW power consumption. The layout size of the CML core is about $91{\times}98\;um^2$. Cascading the Miller and CML frequency dividers, we confirmed the divide-by-4 operation for the input signal from 20 to 25 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.7
• /
• pp.7-15
• /
• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.121-126
• /
• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37 no.8A
• /
• pp.712-719
• /
• 2012

This paper presents Single-bit Third order Delta-Sigma Modulator, which can be applied to the Low speed High resolution ADC in Audio signal Process System. Whereas the Operational Amplifier in modulator consumed static power dissipation in operating, this modulator used Switching on/off techniques, which makes the Power dissipation of the modulator reduced. Also proposed modulator minimizes frequency characteristic variation by optimizing switch position. And this modulator chooses Single-bit type to guarantee stability. The designed ADC went through 0.35um CMOS n-well 1-poly 4-metal process to be a final product, and the final product has shown 17.1mW of power dissipation with 3.3V of Supply Voltage, 6.4MHz of conversion rate. And 84.3dB SNDR and 13.5bit ENOB with 20KHz of input frequency.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.24 no.5
• /
• pp.457-461
• /
• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.229-237
• /
• 2011

In this paper, a 60 GHz LTCC SiP with low-power CMOS OOK modulator and demodulator is presented. The 60 GHz modulator is designed in a 90-nm CMOS process. The modulator uses a current reuse technique and only consumes 14.4-mW of DC power in the on-state. The measured data rate is up to 2 Gb/s. The 60 GHz OOK demodulator is designed in a 130nm CMOS process. The demodulator consists of a gain boosting detector and a baseband amplifier, and it recovers up to 5 Gb/s while consuming low DC power of 14.7 mW. The fabricated 60 GHz modulator and demodulator are fully integrated in an LTCC SiP with 1 by 2 patch antenna. With the LTCC SiP, 648 Mb/s wireless video transmission was successfully demonstrated at wireless distance of 20-cm.

• Journal of the Microelectronics and Packaging Society
• /
• v.16 no.1
• /
• pp.21-25
• /
• 2009

By using Si CMOS process, small RFID tag antenna were fabricated on Si substrate and their electrical properties were evaluated. Firstly, tag antenna pattern and the electromagnetic properties were simulated with HFSS. The frequency was 13.56 MHz, the line-width and line-gap were modeled in the range of $50{\sim}200{\mu}m$. S parameters, SRF, and Q value were calculated from geometry. When the line-width and line-gap were $100{\mu}m$ and $100 {\mu}m$, respectively and the loop-turn was 10, the SRF was 80 MHZ and the Q value was ca. 9. When the microstrip antenna pattern of aluminum $2{\mu}m$ was fabricated by using DC sputtering, Vpp of ca. 4.3 V was obtained when the reader and tag were closely contacted.

• Journal of IKEEE
• /
• v.24 no.4
• /
• pp.1074-1080
• /
• 2020

This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

• ETRI Journal
• /
• v.34 no.6
• /
• pp.885-891
• /
• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.1-7
• /
• 2007

This paper proposes CMOS semi-digital data recovery with 2X converse oversampling to reduce power consumption and chid area of high definition multimedia interface (HDMI) receivers. Proposed recovery can reduce its power and the effective area by using nt converse oversampling algorithm and semi-digital architecture. Proposed circuit is fabricated using 0.18um CMOS process and measured results demonstrated the power consumption of 14.4mW, the effective area of $0.152mm^2$ and the jitter tolerance of 0.7UIpp with 1.8V supply voltage.)