• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.25-29
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• 2002

There is an increasing interest in high-speed signal processing in modern telecommunication and SC circuit, HDTV, ISDN. There are many methods of high-speed signal processing. This paper describes a design approach for the realization of high-frequency Op-amp in CMOS technology. A limiting factor in Op-amp based analog integrated circuits is the limited useful frequency range. this thesis will develop a CMOS op-amp architecture with improved gainband width product with this technique an op-amp will achieve up to 170MHz (CL=2pF) unity-gain frequency with a 1.2-micron design rule. This CMOS op-amp is particularly suitable for achieving wide and stable closed-loop band widths, such as required in high-frequency SC filters, high-speed analog circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.118-123
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• 1989

In this paper, as we have integrated SCF for voice signal processing using CMOS circuit with the low power dissipation and the easy circuit design, it has been presented the simplified CMOS OP AMP design method with ${\pm}$5V pwoer source in order to use together with digital part. After an example about SCF CMOS OP AMP design, it has been performed layout appling channel width and length obtained by design method, and then its characteristics were simulated by SPICE 2G program. Therefoe, this design method will be applied the general CMOS OP AMP design in the electronic circuit.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1108-1110
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• 1995

This paper presents a balanced CMOS complementary folded cascode OP-AMP topology that achieves improved DC gain using the gain boosting technique, a high unity-gain frequency and improved slew rate using the CMOS complementary cascode structure and a high PSRR using the balanced output stage. Bode-plot measurements of a balanced CMOS complementary folded cascode OP-AMP show a DC gain of 80dB, a unity-gain frequency of 110MHz and a slew rate of $274V/{\mu}s$(1pF load). This balanced CMOS complementary folded cascode OP-AMP is well suited for high frequency analog signal processing applications.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.4
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• pp.461-466
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• 1999

A CMOS op amp with rail-to-rail input and output ranges is designed in a one-volt supply. The output stage of the op amp is used in a common source amplifier that operates in sub-threshold region to design a low voltage op amp with rail-to-tail output range. To drive heavy resistor and capacitor loads with rail-to-rail output ranges, a common source amplifier which has a low output resistance is utilized. A bulk-driven differential pair and a bulk-driven folded cascode amplifier are used in the designed op amp to increase input range and achieve 1 V operation. Post layout simulation results show that low frequency gain is about 58 ㏈ and gain bandwidth I MHz. The designed op amp has been fabricated in a 0.8${\mu}{\textrm}{m}$ standard CMOS process. The measured results show that this op amp provides rail-to-rail output range, 56㏈ dc gain with 1 MΩ load and has 0.4 MHz gain-bandwidth with 130 ㎊ and 1 kΩ loads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.768-776
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• 2014

Using a simplified high-frequency small-signal equivalent circuit model for BSIM3 MOSFET, the fully differential two-stage folded-cascode CMOS operational amplifier is analyzed to obtain its small-signal voltage transfer function. As a result, the expressions for dc gain, five zero frequencies, five pole frequencies, unity-gain frequency, and phase margin are derived for op amp design using design equations. Then the analysis result is verified through the comparison with Spice simulations of both a high speed op amp and a low power op amp designed for the $0.13{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.61-66
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• 2007

A gain enhancement rail-to-rail buffer amplifier for liquid crystal display (LCD) source driver is proposed. An op-amp with extremely high gain is needed to decrease the offset voltage of the buffer amplifier. Cascoded floating current source and class-AB control block in the op-amp achieve a high voltage gain by reducing the channel length modulation effect in high voltage technologies. HSPICE simulation in $1\;{\mu}V$ 15 V CMOS process demonstrates that voltage gain is increased by 30 dB. The offset voltage is improved from 6.84 mV to $400\;{\mu}V$. Proposed op-amp is fabricated in an LCD source driver IC and overall system offset voltage is decreased by 2 mV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.873-876
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• 2005

This paper presents a new current transient test technique for wideband CMOS Op Amps. This technique monitors the transient power supply current and output responses of the CMOS Op Amp to automatically differentiate faulty and fault-free op amps. The wideband op amp is designed using 0.25${\mu}$m CMOS technology. We present detailed simulation results for a wideband op amp. We show that catastrophic faults in op amps can be detected and analyzed by monitoring power supply currents and output responses. This technique is inexpensive and simple.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.4
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• pp.602-610
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• 1993

The DDA of new active element and the DDA differential integrator are designed. The DDA can be improved matching problems of external elements in op-amp application circuits. The design of DDA is used the transconductance element, differential pair and $2{\mu}m$ design rule. In order to evaluate the performance of the CMOS DDA, we simulated the DDA voltage inverter and the DDA level shifter using the designed CMOS DDA. Furthermore, the grounded resistor and the differential integrator is designed using the CMOS DDA and we found that its characteristics are agreed to OP-AMP differential integrator's. We performed the layout of the CMOS DDA and DDA differential integrator with MOSIS $2{\mu}m$ CMOS technology.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.39-45
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• 1997

This study presents the first experimental data for the impact of hot-carrier degradtion on the performance of CMOS folded-cascode op-amps. A folded-cascode op-amp which has an NMOS input pair has been designed and fabricated using a 0.8.mu.m single-poly, double-metal CMOS process. After high voltage stress, the degradtion of perfomrance parameters such as open-metal CMOS process. After high voltage stress, the degradation of performance parameters such as open-loop voltage gain, unity-gain frequency and phase margin has been analized and physically explaniend in terms of hot carrier degradation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.