• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.3
• /
• pp.200-209
• /
• 2008

This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.3
• /
• pp.55-60
• /
• 2014

For an high speed communication, a 40GHz VCO was implemented using a 0.11um standard CMOS technology. The mm-wave VCO was designed by a LC type using a spiral inductor, and a simplified architecture with buffers and a smart biasing technique were used to get a high performance. The frequency range of the proposed VCO is 34~40GHz which is suitable for mm-Wave communication system. It has an output power of -16dBm and 16% tuning range. And the phase noise is -100.33dBc/Hz at 1MHz offset at 38GHz fundamental frequency. The total power consumption of VCO including PADs is 16.8mW with 1.2V supply voltage. The VCO achieves the FOMT of -183.8dBc/Hz which is better than previous VOCs.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.3
• /
• pp.399-405
• /
• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• Journal of IKEEE
• /
• v.13 no.2
• /
• pp.118-125
• /
• 2009

With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.503-504
• /
• 2006

This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) using 1-poly 6-metal mixed signal CMOS process. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect from image current of resistive Si substrate. Moreover, due to the incapability of using thick top metal layer of which the thickness is over $2{\mu}m$, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via materials along the metal traces is adopted. The circuit operated from 2.63 GHz to 3.09 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 460 MHz. The measured phase noise was -115 dBc/Hz @ 1MHz offset at 2.63 GHz carrier frequency and the current consumption and the corresponding power consumption were about 2.6 mA and 4.68 mW respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.2
• /
• pp.83-87
• /
• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.1
• /
• pp.131-137
• /
• 2014

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of $1385{\times}835{\mu}m^2$.

• Proceedings of the KIEE Conference
• /
• 2005.07c
• /
• pp.2333-2335
• /
• 2005

Various CMOS quadrature-voltage-controlled oscillators(QVCOs) are designed and fabricated for the comparison of the phase noise. The core VCO is composed of two Colpitts oscillators which are cross-coupled with PMOS pair. For the comparison of phase noise with the proposed scheme, the conventional LC VCO followed by the frequency-divide-by-two is designed. The simulation result demonstrate that the proposed scheme shows better phase noise performance by 6dB than that of a conventional scheme in which LC VCO is followed by the frequency-divide-by-two.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.5
• /
• pp.8-15
• /
• 2002

We optimally designed the VCO(voltage-controlled oscillator) with spiral inductor using the MOSIS HP 0.5${\mu}{\textrm}{m}$ CMOS process. With the developed SPICE model of spiral inductor, the quality factor of spiral inductor was maximized at the operating frequency by varying the layout parameters, e.g., metal width, number of turns, radius, space of the metal lines. For the operation frequency of 2㎓, the inductance of about 3nH, and the MOSIS HP 0.5 CMOS process with the metal thickness of 0.8${\mu}{\textrm}{m}$, oxide thickness of 3${\mu}{\textrm}{m}$, the optimal width of metal lines is about 20${\mu}{\textrm}{m}$ for the maximum Quality factor. With the optimized spiral inductor, the VCO with LC tuning tank was designed, fabricated and measured. The measurements were peformed on-wafer using the HP8593E spectrum analyzer. The oscillation frequency was about 1.610Hz, the frequency variation of 250MHz(15%) with control voltage of 0V - 2V, and the phase noise of -108.4㏈c(@600KHz) from output spectrum.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2003.11a
• /
• pp.234-238
• /
• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.