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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Design of a 0.18$\mu$m CMOS 10Gbps CDR With a Quarter-Rate Bang-Bang Phase Detector

Quarter-Rate Bang-Bang 위상검출기를 사용한 0.18$\mu$m CMOS 10Gbps CDR 회로 설계

  • Cha, Chung-Hyeon (Dept. of Electronic Engineering, University of Incheon) ;
  • Ko, Seung-O (Dept. of Electronic Engineering, University of Incheon) ;
  • Seo, Hee-Taek (Dept. of Electronic Engineering, University of Incheon) ;
  • Park, Jong-Tae (Dept. of Electronic Engineering, University of Incheon) ;
  • Yu, Chong-Gun (Dept. of Electronic Engineering, University of Incheon)
  • Published : 2009.06.30
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Abstract

With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

통신시스템에서 데이터 전송이 고속으로 이루어지면서, 하드웨어의 복잡성, 전력소모, 가격 등의 이유로 클럭을 제외한 데이터만 수신단으로 보내는 방식이 사용되어지고 있다. 따라서, 고속으로 수신된 데이터에서 클럭 신호를 추출하는 것이 필요하며, 추출된 클럭을 이용하여 데이터를 복원하는 클럭/데이터 복원회로(CDR)에 관한 연구가 활발히 이루어지고 있다. 본 논문에서는 0.18um CMOS 공정을 이용하여 10Gbps CDR 회로를 설계하였다. 전력소모와 회로의 복잡도를 줄이기 위해 quarter-rate bang-bang 유형의 위상 검출기를 사용하였으며, 지터 특성 향상을 위해 LC 유형의 4단 VCO를 사용하였다. 모의실험 결과, 설계된 CDR 회로는 1.8V 전원전압에서 80mW의 전력을 소모하며, 2.2ps,pp의 클럭 지터 특성을 보인다. 패드를 제외한 칩 레이아웃 면적은 1.26mm$\times$1.05mm이다.

Keywords

References

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