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http://dx.doi.org/10.5573/JSTS.2008.8.3.200

A Continuously Tunable LC-VCO PLL with Bandwidth Linearization Techniques for PCI Express Gen2 Applications  

Rhee, Woo-Geun (IBM Thomas J. Watson Research Center)
Ainspan, Herschel (IBM Thomas J. Watson Research Center)
Friedman, Daniel J. (IBM Thomas J. Watson Research Center)
Rasmus, Todd (IBM, Research Triangle Park)
Garvin, Stacy (IBM, Research Triangle Park)
Cranford, Clay (IBM, Research Triangle Park)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.8, no.3, 2008 , pp. 200-209 More about this Journal
Abstract
This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.
Keywords
PLL; tunable LC-VCO; PCI Express Gen2; bandwidth linearization;
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