• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.483-485
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• 2010

A 200kS/s 10-bit successive approximation(SA) ADC with a rail-to-rail input range is proposed. The proposed SA ADC consists of DAC, comparator, and successive approximation register(SAR) logic. The folded-type capacitor DAC with the boosted NMOS switches is used to reduce the power consumption and chip area. Also, the time-domain comparator which uses a fully differential voltage-to-time converter improves the PSRR and CMRR. The SAR logic uses the flip-flop with a half valid window, it results in the reduction of the power consumption and chip area. The proposed SA ADC is designed by using a $0.18{\mu}m$ CMOS process with 1V supply.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.15-22
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• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.414-422
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• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.19-29
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• 2003

This paper proposes a CMOS readout circuit for uncooled micro-bolometer arrays adopting a four-point step calibration technique. The proposed readout circuit employing an 11b analog-to-digital converter (ADC), a 7b digital-to-analog converter (DAC), and an automatic gain control circuit (AGC) extracts minute infrared (IR) signals from the large output signals of uncooled micro-bolometer arrays including DC bias currents, inter-pixel process variations, and self-heating effects. Die area and Power consumption of the ADC are minimized with merged-capacitor switching (MCS) technique adopted. The current mirror with high linearity is proposed at the output stage of the DAC to calibrate inter-pixel process variations and self-heating effects. The prototype is fabricated on a double-poly double-metal 1.2 um CMOS process and the measured power consumption is 110 ㎽ from a 4.5 V supply. The measured differential nonlinearity (DNL) and integrat nonlinearity (INL) of the 11b ADC show $\pm$0.9 LSB and $\pm$1.8 LSB, while the DNL and INL of the 7b DAC show $\pm$0.1 LSB and $\pm$0.1 LSB.