• Progress in Medical Physics
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• v.27 no.1
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• pp.1-7
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• 2016

In this work, we considered a compressed-sensing (CS)-based image deblurring scheme with a total-variation (TV) regularization penalty for improving image characteristics in digital tomosynthesis (DTS). We implemented the proposed image deblurring algorithm and performed a systematic simulation to demonstrate its viability. We also performed an experiment by using a table-top setup which consists of an x-ray tube operated at $90kV_p$, 6 mAs and a CMOS-type flat-panel detector having a $198-{\mu}m$ pixel resolution. In the both simulation and experiment, 51 projection images were taken with a tomographic angle range of ${\theta}=60^{\circ}$ and an angle step of ${\Delta}{\theta}=1.2^{\circ}$ and then deblurred by using the proposed deblurring algorithm before performing the common filtered-backprojection (FBP)-based DTS reconstruction. According to our results, the image sharpness of the recovered x-ray images and the reconstructed DTS images were significantly improved and the cross-plane spatial resolution in DTS was also improved by a factor of about 1.4. Thus the proposed deblurring scheme appears to be effective for the blurring problems in both conventional radiography and DTS and is applicable to improve the present image characteristics.

• Journal of the Korean earth science society
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• v.34 no.6
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• pp.588-601
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• 2013

In geophysics and geophysical exploration fields, we can use information about inclination and azimuth in various ways. These include borehole deviation logging for inversion process, real-time data acquisition system, geophysical monitoring system, and so on. This type of information is also necessarily used in the directional drilling of shale gas fields. We thus need to develop a subminiature, low-powered, multi-functional inclination and azimuth measurement system for geophysical exploration fields. In this paper, to develop real-time measurement system, we adopt the high performance low power Micro Control Unit (made with state-of-the-art Complementary Metal Oxide Semiconductor technology) and newly released Micro Electro Mechanical Systems Attitude Heading Reference System sensors. We present test results on the development of a multifunctional real-time inclination and azimuth measurement system. The developed system has an ultra-slim body so as to be installed in 42mm sonde. Also, this system allows us to acquire data in real-time and to easily expand its application by synchronizing with a depth encoder or Differential Global Positioning System.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.410-410
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• 2013

Next-generation nonvolatile memory (NVM) has attracted increasing attention about emerging NVMs such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory and resistance random access memory (RRAM). Previous studies have demonstrated that RRAM is promising because of its excellent properties, including simple structure, high speed and high density integration. Many research groups have reported a lot of metal oxides as resistive materials like TiO2, NiO, SrTiO3 and ZnO [1]. Among them, the ZnO-based film is one of the most promising materials for RRAM because of its good switching characteristics, reliability and high transparency [2]. However, in many studies about ZnO-based RRAMs, there was a problem to get lower current level for reducing the operating power dissipation and improving the device reliability such an endurance and an retention time of memory devices. Thus in this paper, we investigated that highly reproducible bipolar resistive switching characteristics of W doped ZnO RRAM device and it showed low resistive switching current level and large ON/OFF ratio. This may be caused by the interdiffusion of the W atoms in the ZnO film, whch serves as dopants, and leakage current would rise resulting in the lowering of current level [3]. In this work, a ZnO film and W doped ZnO film were fabricated on a Si substrate using RF magnetron sputtering from ZnO and W targets at room temperature with Ar gas ambient, and compared their current levels. Compared with the conventional ZnO-based RRAM, the W doped ZnO ReRAM device shows the reduction of reset current from ~$10^{-6}$ A to ~$10^{-9}$ A and large ON/OFF ratio of ~$10^3$ along with self-rectifying characteristic as shown in Fig. 1. In addition, we observed good endurance of $10^3$ times and retention time of $10^4$ s in the W doped ZnO ReRAM device. With this advantageous characteristics, W doped ZnO thin film device is a promising candidates for CMOS compatible and high-density RRAM devices.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.329-335
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• 2010

Digital imaging detectors can use a variety of detection materials to convert X-ray radiation either to light or directly to electron charge. Many detectors such as amorphous silicon flat panels, CCDs, and CMOS photodiode arrays incorporate a scintillator screen to convert x-ray to light. The digital radiography systems based on semiconductor detectors, commonly referred to as flat panel detectors, are gaining popularity in the clinical & hospital. The X-ray detectors are described between a-Silicon based indirect type and a-Selenium based direct type. The DRS of detectors is used to convert the x-ray to electron hole pairs. Image processing is described by specific image features: Latitude compression, Contrast enhancement, Edge enhancement, Look up table, Noise suppression. The image features are tuned independently. The final enhancement result is a combination of all image features. The parameters are altered by using specific image features in the different several hospitals. The image in a radiological report consists of two image evaluation processes: Clinical image parameters and MTF is a descriptor of the spatial resolution of a digital imaging system. We used the edge test phantom and exposure procedure described in the IEC 61267 to obtain an edge spread function from which the MTF is calculated. We can compare image in the processing parameters to change between original and processed image data. The angle of the edge with respect to the axes of detector was varied in order to determine the MTF as a function of direction. Each MTF is integrated within the spatial resolution interval of 1.35-11.70 cycles/mm at the 50% MTF point. Each image enhancement parameters consists of edge, frequency, contrast, LUT, noise, sensitometry curve, threshold level, windows. The digital device is also shown to have good uniformity of MTF and image parameters across its modality. The measurements reported here represent a comprehensive evaluation of digital radiography system designed for use in the DRS. The results indicate that the parameter enables very good image quality in the digital radiography. Of course, the quality of image from a parameter is determined by other digital devices in addition to the proper clinical image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.366-372
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• 2017

In this paper, the analysis of baluns that are inevitably required to design a differential low noise amplifier, The balun converts a single signal input from the antenna into a differential signal, which serves as an input to the differential amplifier. In addition, it protects the circuit from ESD(Electrostatic Discharge) coming through the antenna and helps with input matching. However, in the case of a passive balun used in general, since the AC signal is transmitted through electromagnetic coupling formed between two metal lines, it not only has loss without gain but also has the greatest influence on the total noise figure of the receiving end. Therefore, the design of a balun in a low-noise amplifier is very important, and it is important to design a balun in consideration of line width, line spacing, winding, radius, and layout symmetry that are necessary. In this paper, the factors to be considered for improving the quality factor of balun are summarized, and the tendency of variation of resistance, inductance, and capacitance of the balun according to design element change is analyzed. Based on the analysis results, it is proved that the design of input balun allows the design of low noise, high gain differential amplifier with gain of 24 dB and noise figure of 2.51 dB.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.10-10
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• 2008

Silicide is inevitable for CMOSFETs to reduce RC delay by reducing the sheet resistance of gate and source/drain regions. Ni-silicide is a promising material which can be used for the 65nm CMOS technologies. Ni-silicide was proposed in order to make up for the weak points of Co-silicide and Ti-silicide, such as the high consumption of silicon and the line width limitation. Low resistivity NiSi can be formed at low temperature ($\sim500^{\circ}C$) with only one-step heat treat. Ni silicide also has less dependence of sheet resistance on line width and less consumption of silicon because of low resistivity NiSi phase. However, the low thermal stability of the Ni-silicide is a major problem for the post process implementation, such as metalization or ILD(inter layer dielectric) process, that is, it is crucial to prevent both the agglomeration of mono-silicide and its transformation into $NiSi_2$. To solve the thermal immune problem of Ni-silicide, various studies, such as capping layer and inter layer, have been worked. In this paper, the Ni-silicide utilizing Pd stacked layer (Pd/Ni/TiN) was studied for highly thermal immune nano-scale CMOSFETs technology. The proposed structure was compared with NiITiN structure and showed much better thermal stability than Ni/TiN.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.