전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제49권12호
  • /
  • Pages.184-193
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  • 2012
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  • 2287-5026(pISSN)
  • /
  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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채널 등화기를 내장한 2.0GS/s 5비트 전류 모드 ADC 기반 수신기

A 2.0-GS/s 5-b Current Mode ADC-Based Receiver with Embedded Channel Equalizer

  • 문종호 (성균관대학교 정보통신대학) ;
  • 정우철 (성균관대학교 정보통신대학) ;
  • 김진태 (건국대학교 전자공학부) ;
  • 권기원 (성균관대학교 정보통신대학) ;
  • 전영현 (삼성전자(주) 반도체사업부) ;
  • 전정훈 (성균관대학교 정보통신대학)
  • Moon, Jong-Ho (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Jung, Woo-Chul (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, Jin-Tae (Department of Electronics Engineering, Konkuk University) ;
  • Kwon, Kee-Won (College of Information & Communication Engineering, Sungkyunkwan University) ;
  • Jun, Young-Hyun (Device Solution Business, Samsung Electronics) ;
  • Chun, Jung-Hoon (College of Information & Communication Engineering, Sungkyunkwan University)
  • 투고 : 2012.09.11
  • 발행 : 2012.12.25
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초록

본 논문에서는 고속 직렬 링크에 사용할 수 있는 5비트 2.0GS/s 2-way time interleaved 파이프라인 ADC 기반의 수신기를 소개한다. 샘플링 주파수를 높이기 위해, ADC 각 단은 트랙킹과 증폭이 동시에 수행되는 전류 모드 구조를 사용하였다. 또한 ADC 각단에 1-tap FIR 등화기를 탑재하여 별도의 디지털 후처리 없이 채널의 ISI를 감소시켰다. 제안한 수신기는 110nm 공정을 사용하여 설계하였다. 메모리를 제외한 수신기는 $0.58{\times}0.42mm^2$의 크기를 갖고, 동작전압 1.2V에서 91mW의 전력을 소모한다. 시뮬레이션 결과 2.0GS/s 샘플링 주파수에서 20MHz의 입력 주파수와 Nyquist 주파수인 1.0GHz 입력신호에 대하여 동일하게 26.0dB의 SNDR과 4.0비트의 ENOB특성을 확보하였다.

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

키워드

참고문헌

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