• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.48-51
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• 2009

One-stage low noise amplifier (LNA) using 65 nm RF CMOS technology below 20 GHz is designed to find the optimal bias voltage and optimal width of input transistor so that the maximum figure of merit (FoM) has been achieved. If the frequency is higher than 13 GHz, the amplifier needs two-stage to achieve the higher gain. If the frequency is lower than 5 GHz, one additional capacitor between gate and source should be added to control the power under the limitation. This paper summarizes one-stage LNA overall performances below 20 GHz and this approach can also be applied to other CMOS technology of LNA designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1927-1934
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• 2016

In this paper, we proposed a I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistor) structure in order to mitigate a radiation-induced leakage current path in an isolation oxide interface of a silicon-based standard n-MOSFET. The proposed I-gate n-MOSFET structure was designed by using a layout modification technology in the standard 0.18um CMOS (Complementary Metal Oxide Semiconductor) process, this structure supplements the structural drawbacks of conventional radiation-tolerant electronic device using layout modification technology such as an ELT (Enclosed Layout Transistor) and a DGA (Dummy Gate-Assisted) n-MOSFET. Thus, in comparison with the conventional structures, it can ensure expandability of a circuit design in a semiconductor-chip fabrication. Also for verification of a radiation-tolerant characteristic, we carried out M&S (Modeling and Simulation) using TCAD 3D (Technology Computer Aided Design 3-dimension) tool. As a results, we had confirmed the radiation-tolerant characteristic of the I-gate n-MOSFET structure.

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1932-1938
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• 2003

We have applied spectroscopic ellipsometry to investigate $high-{\kappa}$ dielectric thin films and correlate their optical properties with fabrication processes, in particular, with high temperature annealing. The use of high-k dielectrics such as $HfO_{2}$, $Ta_{2}O_{5}$, $TiO_{2}$, and $ZrO_{2}$ as the replacement for $SiO_{2}$ as the gate dielectric in CMOS devices has received much attention recently due to its high dielectric constant. From the characteristics found in the pseudo-dielectric functions or the Tauc-Lorentz dispersions, the optical properties such as optical band gap, polycrystallization, and optical density will be discussed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.765-767
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• 2007

본 연구에서는 Sentaurus의 Tecplot를 이용한 FinFET를 구현 하고자 한다. FinFET구조를 간략히 설명하면 소자의 성능 향상과 누설전류의 최소화를 지속하기 위해 한면에 하나씩 두개의 게이트가 사용되어 소자의 전환을 쉽게 해준다. 이러한 구조 때문에 이중게이트 MOSFET라고 불린다 CMOS소자는 수평적으로 구성되지만 FinFET는 수직적으로 구성이 된 구조이다. FinFET 구조를 Sentaurus의 Tecplot를 사용하여 복잡한 데이터를 분석, 탐색하고 다중 XY, 2D, 3D plot를 배치하고 분석할 수 있다. Tecplot툴의 자동화된 루틴으로 데이터 분석과 plotting에 투입하는 시간을 절약할 수 있다. 본 연구에서는 Sentaurus의 Tecplot 툴을 이용하여 FinFET를 구현 하고자 한다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.505-508
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• 2004

Gate length dependent data of intrinsic MOSFET equivalent circuit parameters are extracted using a direct extraction technique based on simple 2-port parameter equations. The relatively scalable data with respect to gate length are obtained. These data are verified to be acrurate by observing good correspondence between modeled and measured S-parameters up to 30GHz. These data will be helpful to construct RF scalable MOSFET model.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.347-350
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• 2004

The substrate parameters of Si MOSFET equivalent circuit model were directly extracted from measured S-Parameters in the GHz region by using simple 2-port parameter equations. Using the above extract ion method, bias and gate length dependent curves of substrate parameters in the RF region are obtained by varying drain voltage at several short channel devices with various gate lengths. These extract ion data will greatly contribute to scalable RF nonlinear substrate modeling.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.298-310
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• 1997

Most of the available delay fault simulators for scan environments rely on the use of enhanced scan flip-flops and exclusively consider circuits composed of only discrete gates. In this research, a new path delay fault simulation algorithm using new logic values is devised to enlarge the scope to the VLSI circuits which consist of CMOS elements. Based on the proposed algorithm, a high speed path delay fault simulator for standard scan environments is developed. The experimental results show the new simulator is efficient and accurate.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.92-96
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• 1999

As CMOS technologies have been rapidly developed, bridging faults have been relatively increased. IDDQ testing is a current testing methodology which can enhance reliability of the circuit since it efficiently detects bridging faults that are difficult to detect by functional testing. In this paper we consider internal bridging faults occurred in each gate of logic circuits under test and finally develop a fault simulator for IDDQ testing to detect assumed bridging faults.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.579-580
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• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.