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Design Optimization of a One-Stage Low Noise Amplifier below 20 GHz in 65 nm CMOS Technology  

Shen, Ye-Hao (School of Electrical Engineering and Computer Science, Seoul national University)
Lee, Jae-Hong (School of Electrical Engineering and Computer Science, Seoul national University)
Shin, Hyung-Cheol (School of Electrical Engineering and Computer Science, Seoul national University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.6, 2009 , pp. 48-51 More about this Journal
Abstract
One-stage low noise amplifier (LNA) using 65 nm RF CMOS technology below 20 GHz is designed to find the optimal bias voltage and optimal width of input transistor so that the maximum figure of merit (FoM) has been achieved. If the frequency is higher than 13 GHz, the amplifier needs two-stage to achieve the higher gain. If the frequency is lower than 5 GHz, one additional capacitor between gate and source should be added to control the power under the limitation. This paper summarizes one-stage LNA overall performances below 20 GHz and this approach can also be applied to other CMOS technology of LNA designs.
Keywords
low noise amplifier (LNA); figure of merit (FoM); noise figure;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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