• Journal of Pharmaceutical Investigation
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• v.5 no.2
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• pp.57-62
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• 1975

It was many differances to evaluate of the effect of excipients on colour fading in FD & C Yellow No.5 by use Tintometer and nearly is not effective in FD & C Red No. 2. When we observed colour fading in suger coating formulations by tintometer, FD & C Red No.2 was appeared to follow zero order reaction and FD & C Yellow No. 5 was not follow zero order reaction or first order reaction. Also, we could know the tendency of colour fading by visible spectrum, but it was net suitable method for this experiment more than by tintometer. The relative colour fading effect of the surfactants(Polysorbate) was as follows: Tween 60> Tween 80> Tween 20. In addition to, Benzalkonium chloride was reacted with FD & C Yellow No.5, so the stronger colour was appeared. On the other hand, the weaker colour was appeared in FD & C Red No.2. While, the sunscreening agents was not almost effective in colour fading of FD & Yellow No. 5 and FD & C Red No. 2.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.25-32
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• 2011

NoC is actively being studied recently in order to overcome the limitations of shared-bus architecture. We proposed an NoC architecture which employs a buffer that plays a similar role of a proxy server in a computer network to enhance the communication efficiency of NoC architecture. In the proposed NoC architecture, whenever the master has a difficulty in communicating with the slave directly, the master communicates with the proxy server which is able to communicate with the slave on behalf of the master. With the proposed scheme in NoC, we can increase the speed and the bandwidth of communication channel. The experimental results showed that overall communication efficiency was significantly improved by sending the packets to the proxy server rather than holding them in the switch buffer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.359-366
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• 2016

Today's multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.

• Journal of KIISE
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• v.43 no.2
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• pp.163-176
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• 2016

The contention overhead on the same channel in an NoC architecture can significantly increase a communication delay due to the simultaneous communication requests that occur. To reduce the overall overhead, we propose task-to-tile binding techniques for an NoC-based manycore platform, whereby it is assumed that the task mapping decision has already made. Since the NoC architecture may have multiple memory tiles as its size grows, memory clustering is used to balance the load of memory by making applications access different memory tiles. We assume that the information on the communication overhead of each application is known since it is specified in a dataflow task graph. Using this information, this paper proposes two heurisitics that perform binding of multiple tasks at once based on a proper memory clustering method. Experiments with an NoC simulator prove that the proposed heurisitic shows performance gains that are 25% greater than that of the previous binding heuristic.

• The Korean Journal of Pharmacology
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• v.31 no.1 s.57
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• pp.75-84
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• 1995

Acid secretion and NO synthase activity were determined in isolated gastric glands following hypoxia/reoxygenation and acidosis to investigate the involvement of NO in acid secretion. Isolated gastric glands were exposed to hypoxia (30 min)/reoxygenation (1 h) and/or to acidosis (pH 6.0 and 4.0). Acid secretion was measured by the ratio of $[^{14}C]-aminopyrine$ accumulation between intra- and extraglands. NO synthase activity was determined by percent conversion to $[^{14}C]-citrulline\;from\;[^{14}C]L-arginine$, a precursor of NO. The results indicate that dibutyryl cAMP stimulated acid secretion dose-dependently but had no effect on NO synthase activity in basal gastric glands. Hypoxia/reoxygenation significantly suppressed acid secretion both in unstimulated and stimulated gastric glands, which was exaggerated by acidosis. Constitutive NO synthase, activity, not responded to dibutyryl cAMP, was also inhibited by hypoxia/reoxygenation and acidosis. In conclusion, pathologic state of gastric mucosa such as hypoxia/reoxygenation and acidosis suppresses both acid secretion and NO release but the role of NO in acid secretion stimulated by dibutyryl cAMP in basal gastric glands is not significant.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.25-32
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• 2011

Networks-on-chip (NoC) is emerging as a key technology to overcome severe bus traffics in ever-increasing complexity of the Multiprocessor systems-on-chip (MPSoC); however traditional electrical interconnection based NoC architecture would be faced with technical limits of bandwidth and power consumptions in the near future. In order to cope with these problems, a hybrid optical NoC architecture which use both electrical interconnects and optical interconnects together, has been widely investigated. In the hybrid optical NoCs, wormhole switching and simple deterministic X-Y routing are used for the electrical interconnections which is responsible for the setup of routing path and optical router to transmit optical data through optical interconnects. Optical NoC uses circuit switching method to send payload data by preset paths and routers. However, conventional hybrid optical NoC has a drawback that concurrent transmissions are not allowed. Therefore, performance improvement is limited. In this paper, we propose a new routing algorithm that uses circuit switching and adaptive algorithm for the electrical interconnections to transmit data using multiple paths simultaneously. We also propose an efficient method to prevent livelock problems. Experimental results show up to 60% throughput improvement compared to a hybrid optical NoC and 65% power reduction compared to an electrical NoC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.86-94
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• 2007

The NoC (network-on-chip) approach is a promising solution to the increasing complexity of on-chip communication problems because of its high scalability. But, NoC applications generally consume a lot of power, because they require a large design space to accommodate many parallel IPs and network communication channels. It is not easy to analyze the power consumption of NoC applications with conventional simulation methods using simple power models. In addition, there are also many limitations in using sophisticated simulation models because they require long execution time and large efforts. In this paper, we apply a cycle-accurate energy measurement technique and tool to the FPGA prototypes, which are generally used to verify the correctness of SoC designs, as a practical indication of the power consumption of real NoC applications. An NoC-based JPEG encoder implementation is used as a case study to demonstrate the effectiveness of our approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.71-78
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• 2006

An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.56-65
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• 2009

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.117-123
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• 2008

In this paper, we propose a novel ant colony optimization(ACO)-based application core ma ins method for implementing network-on-chip(NoC)-based systems-on-chip(SoCs). The proposed method efficiently put application cores to a mesh-type NoC satisfying a given design objective, the network latency. Experimental results using a functional circuit including 12 cores show that the proposed algorithm can produce near optimal mapping results within a second.