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NoC Test Scheduling Based on a Rectangle Packing Algorithm  

Ahn Jin-Ho (Yonsei Univ. Electrical and Electronic Engineering)
Kim Gunbae (Yonsei Univ. Electrical and Electronic Engineering)
Kang Sungho (Yonsei Univ. Electrical and Electronic Engineering)
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Abstract
An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.
Keywords
NoC; Rectangle Packing;
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