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Design and Implementation of On-Chip Network Architecture for Improving Latency Efficiency  

Jo, Seong-Min (Department of Electronics and Computer Engineering, Hanyang University)
Cho, Han-Wook (Department of Electronics and Computer Engineering, Hanyang University)
Ha, Jin-Seok (Department of Electronics and Computer Engineering, Hanyang University)
Song, Yong-Ho (Department of Electronics and Computer Engineering, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.11, 2009 , pp. 56-65 More about this Journal
Abstract
As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).
Keywords
SoC; NoC; ESL; low latency; on-chip network;
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