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Application Core Mapping to Minimize the Network Latency on Regular NoC Architectures  

Ahn, Jin-Ho (Hoseo Univ., Electronic Engineering)
Kim, Hong-Sik (Yonsei Univ., Electrical&Electronic Engineering)
Kim, Hyun-Jin (Yonsei Univ., Electrical&Electronic Engineering)
Park, Young-Ho (ETRI, Network Tech. Lab., NoC Tech. Team)
Kang, Sung-Ho (Yonsei Univ., Electrical&Electronic Engineering)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.4, 2008 , pp. 117-123 More about this Journal
Abstract
In this paper, we propose a novel ant colony optimization(ACO)-based application core ma ins method for implementing network-on-chip(NoC)-based systems-on-chip(SoCs). The proposed method efficiently put application cores to a mesh-type NoC satisfying a given design objective, the network latency. Experimental results using a functional circuit including 12 cores show that the proposed algorithm can produce near optimal mapping results within a second.
Keywords
NoC; Application Core Mapping; Ant Colony Optimization;
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  • Reference
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