NoC Test Scheduling Based on a Rectangle Packing Algorithm

Rectangle Packing 방식 기반 NoC 테스트 스케쥴링

  • Ahn Jin-Ho (Yonsei Univ. Electrical and Electronic Engineering) ;
  • Kim Gunbae (Yonsei Univ. Electrical and Electronic Engineering) ;
  • Kang Sungho (Yonsei Univ. Electrical and Electronic Engineering)
  • 안진호 (연세대학교 전기전자공학과) ;
  • 김근배 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2006.01.01

Abstract

An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.

NoC 테스트는 온칩네트워크를 TAM으로 재사용하기 때문에 SoC 구조 기반의 여러 테스트 기법을 그대로 사용할 수가 없다. 본 논문에서는 네트워크 기반 TAM의 문제점을 크게 감소시킨 새로운 형태의 NoC 테스트 플랫폼을 소개하며 이를 이용한 NoC 테스트 스케줄링 알고리즘을 제안한다. 제안한 알고리즘은 SoC 테스트 용도로 개발된 rectangle packing 방식을 기반으로 효율적이고 체계적인 테스트 스케줄링이 가능하게 한다. ITC'02 벤치회로를 이용한 실험 결과 제안한 방법이 기존 방법에 비해 최대 $55\%$까지 테스트 시간을 줄일 수 있음을 확인하였다.

Keywords

References

  1. L. Benini and G. D. Micheli, 'Networks on Chips: A New SoC Paradigm,' IEEE Computer, Vol 35, pp. 70-78, Jan. 2002 https://doi.org/10.1109/2.976921
  2. P. Guerrier and A. Greiner, 'A Generic Architecture for On-Chip Packet-Switched Interconnections,' Proc. DATE, pp. 250-256, Mar. 2000 https://doi.org/10.1145/343647.343776
  3. B. Vermeulen, J. Dielissen, K. Goossens, and C. Ciordas, 'Bringing Communication Networks on a Chip: Test and Verification Implications,' IEEE Communications Magazine, Vol 41, pp. 74-81, Sep. 2003 https://doi.org/10.1109/MCOM.2003.1232240
  4. M. Nahvi and A. Ivanov, 'Indirect Test Architecture for SoC Testing,' IEEE Trans. on CAD, Vol. 23, No.7, pp. 1128-1142, July 2004 https://doi.org/10.1109/TCAD.2004.829796
  5. K. Chakrabarty, 'Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming,' IEEE Trans. on CAD, pp, 1163-1174, Oct. 2000 https://doi.org/10.1109/43.875306
  6. V. Iyengar, K. Chakrabarty, and E. J. Marinissen, 'On using Rectangle Packing for SOC Wrapper/TAM Co-Optimization,' Proc. VTS, pp.253-258, 2002
  7. W. Zou, S .R. Reddy, I. Pomeranz, and Y. Huang, 'SOC Test Scheduling Using Simulated Annealing,' Proc. VTS, pp. 325-330, April 2003
  8. E. Larsson and Z. Peng, 'A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling,' Proc. ITC, pp. 1135-1144, Sep. 2003 https://doi.org/10.1109/TEST.2003.1271102
  9. E. Larsson and Z. Peng, 'A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling,' Proc. ITC, pp. 1135-1144, Sep. 2003 https://doi.org/10.1109/TEST.2003.1271102
  10. Y. Xia, M. Chrzanowska-Jeske, B. Wang, and M. Jeske,'Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints,' Proc. ICCAD, pp, 100-105, Nov. 2003 https://doi.org/10.1109/ICCAD.2003.148
  11. A. Sehgal and K. Chakrabarty, 'Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures,' Proc. DATE, pp 422-427, Feb. 2004
  12. J. Im, S. Chun, G. Kim, J. Ahn, and S. Kang, 'RAIN(RAndom INsertion) Scheduling Algorithm for SoC Test,' Proc. ATS, pp 242-247, Nov. 2004 https://doi.org/10.1109/ATS.2004.71
  13. C. Liu, V. Iyengar, J. Shi, and E. Cota, 'Power-Aware Test Scheduling in Network-an-Chip Using Variable-Hate On-Chip Clocking,' Proc. VTS, pp. 349-354, May 2005
  14. C. Liu, E. Cota, H. Sharif, and D. K Pradhan, 'Test Scheduling for Network-on-Chip with BIST and Precedence Constraints,' Proc. ITC, pp. 1369-1378, Oct. 2004 https://doi.org/10.1109/TEST.2004.1387412
  15. E. Cota, M. Kreutz, C. A. Zeferino, L. Carro, M. Lubaszewski, and A. Susin, 'The Impact of NoC Reuse on the Testing of Core-based Systems,' Proc. VTS, pp. 128-133, April 2003 https://doi.org/10.1109/VTEST.2003.1197643
  16. E. Cota, L. Carro, F. Wagner, and M. Lubaszewski, 'Power-Aware NoC Reuse on the Testing of Core-Based Systems,' Proc, ITC, Vol. 1, pp. 612-621, Sep. 2003
  17. A. M. Amory, E. Cota, M. Lubaszewski, F. G. Moraes, 'Reducing Test Time with Processor Reuse in Network-on-Chip Based System,' Proc. the 17th Symposium on Integrated Circuits and Systems Design, pp. 111-116, Sep. 2004 https://doi.org/10.1145/1016568.1016602
  18. J. Ahn, B. I. Moon, and S. Kang, 'A Practical Test Scheduling using Network-Based TAM in Network on Chip Architecture,' LNCS, Vol. 3740, pp. 614-624, Oct. 2005 https://doi.org/10.1007/11572961_50
  19. ARM IHI 0011A, AMBA (Rev 2) Specification, ARM Limited, 1999
  20. J. Duato, Interconnection Networks: An Engineering Approach, Morgan Kaufmann Publishers, San Francisco, CA, USA, 2003
  21. J. Marinissen, V. Iyengar and K. Chakrabarty, ITC'02 SoC Test Benchmarks, http://www. hitech-projects.com/itc02socbenchm