Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design and Implementation of On-Chip Network Architecture for Improving Latency Efficiency

지연시간 효율 개선을 위한 On-Chip Network 구조 설계 및 구현

  • Jo, Seong-Min (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Cho, Han-Wook (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Ha, Jin-Seok (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Song, Yong-Ho (Department of Electronics and Computer Engineering, Hanyang University)
  • 조성민 (한양대학교 전자컴퓨터통신공학과) ;
  • 조한욱 (한양대학교 전자컴퓨터통신공학과) ;
  • 하진석 (한양대학교 전자컴퓨터통신공학과) ;
  • 송용호 (한양대학교 전자컴퓨터통신공학과)
  • Published : 2009.11.25
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Abstract

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

최근 SoC의 집적도가 증가함에 따라 칩 내부의 통신 효율성은 시스템 성능에 직접적인 영향을 미치고 있다. 이에 따라 칩내부의 통신 메커니즘은 과거 shared wire를 이용한 버스 시스템에서 라우터를 기반으로 하는 NoC로 진화하고 있다. 하지만, NoC 내부의 라우터는 컨트롤 로직이 복잡해짐에 따라 신호 전달 과정에서 지연시간을 증가시켜 NoC의 성능을 제한시킨다. 따라서 본 논문에서는 이러한 지연시간을 개선시키기 위하여 낮은 복잡도를 갖는 라우터를 제시한다. 제안한 라우터의 구조 검증 및 성능 평가를 위하여 ESL 기법의 시뮬레이션 플랫폼을 구축하였다. 본 논문에서 제안한 NoC 구조는 기존의 VC 라우터 기반의 NoC에 비해 대역폭은 약 1-2% 정도 감소하였지만, 평균적으로 약 50%의 지연시간이 감소 효과를 보였다.

Keywords

References

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