• 제목/요약/키워드: Built-In-Test

검색결과 1,473건 처리시간 0.031초

A New Approach for Built-in Self-Test of 4.5 to 5.5 GHz Low-Noise Amplifiers

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • ETRI Journal
    • /
    • 제28권3호
    • /
    • pp.355-363
    • /
    • 2006
  • This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using $0.18\;{\mu}m$ SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.

  • PDF

플래시 메모리를 위한 유한 상태 머신 기반의 프로그래머블 자체 테스트 (FSM-based Programmable Built-ln Self Test for Flash Memory)

  • 김지환;장훈
    • 대한전자공학회논문지SD
    • /
    • 제44권6호
    • /
    • pp.34-41
    • /
    • 2007
  • 본 논문에서 제안한 FSM 기반의 프로그래머블 BIST(Built-In Self-Test)는 플래시 메모리를 테스트하기 위한 기조의 알고리즘들을 코드화 하여 그 중에서 선택된 알고리즘의 명령어 코드를 받아서 플래시 메모리 테스트를 수행한다. 또한 제안하는 구조는 각 알고리즘에 대한 테스트 절차를 간단하게 한다. 이외에도 플래시 메모리 BIST를 재구성하는데 걸리는 시가도 기조의 BIST와 비교해 볼 때 매우 적다. 우리가 제안한 BIST 구조는 자동적으로 Verilog 코드를 생성해주는 프로그래머블 플래시메모리 BIST 생성기이다. 만약 제안된 방법을 실험하게 되면, 제안된 방법은 이전의 방법들과 비교해서 크기도 더 작을 뿐만 아니라 융통성 면에서도 좋은 성과를 얻었다.

Logic Built In Self Test 구조의 내부 특성 패턴 매칭 알고리즘 (Internal Pattern Matching Algorithm of Logic Built In Self Test Structure)

  • 전유성;김인수;민형복
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2008년도 제39회 하계학술대회
    • /
    • pp.1959-1960
    • /
    • 2008
  • The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

  • PDF

수 Gbps 고속 인터페이스의 오류검출을 위한 자가내장측정법의 가속화 연구 (A Study on Accelerated Built-in Self Test for Error Detecting in Multi-Gbps High Speed Interfaces)

  • 노준완;권기원;전정훈
    • 전자공학회논문지
    • /
    • 제49권12호
    • /
    • pp.226-233
    • /
    • 2012
  • 본 논문에서는 고속 인터페이스 비트오류율(BER, Bit Error Rate)의 수학적 모델을 기반으로, 간단하고 정확하게 시간마진을 추정할 수 있는 '선형 근사화 추정법(linear approximation method)'을 제안하였다. 기존의 Q-factor를 이용한 추정법과 제안한 선형 근사화 추정법을 이용하여 $10^{-13}$ 이하의 BER을 얻기 위한 시간마진을 추정한 결과는 실측한 값과 비교할 때 약 0.03UI 정도의 작은 오차를 갖는다. 이 중 선형 근사화를 이용한 가속 자가내장측정법(built-in self test)을 내부 BERT(BER Tester)를 포함한 하드웨어로 구현하였다. 3Gbps, 95% 신뢰 수준에서 $10^{-13}$ BER 기준의 시간마진을 직접 측정하는데 소요되는 시간이 약 5.6시간인데 반해, 가속 자가내장측정법은 0.6초 이내에 유사한 정확도로 시간마진을 추정한다. 시간마진 추정치는 시간마진을 내부 BERT로 직접 측정한 값과 0.045UI 이하의 작은 오차를 보였다.

Fully Programmable Memory BIST for Commodity DRAMs

  • Kim, Ilwoong;Jeong, Woosik;Kang, Dongho;Kang, Sungho
    • ETRI Journal
    • /
    • 제37권4호
    • /
    • pp.787-792
    • /
    • 2015
  • To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

Retrofitted built-up steel angle members for enhancing bearing capacity of latticed towers: Experiment

  • Wang, Jian-Tao;Wu, Xiao-Hong;Yang, Bin;Sun, Qing
    • Steel and Composite Structures
    • /
    • 제41권5호
    • /
    • pp.681-695
    • /
    • 2021
  • Many existing transmission or communication towers designed several decades ago have undergone nonreversible performance degradation, making it hardly meet the additional requirements from upgrades in wind load design codes and extra services of electricity and communication. Therefore, a new-type non-destructive reinforcement method was proposed to reduce the on-site operation of drilling and welding for improving the quality and efficiency of reinforcement. Six built-up steel angle members were tested under compression to examine the reinforcement performance. Subsequently, the cyclic loading test was conducted on a pair of steel angle tower sub-structures to investigate the reinforcement effect, and a simplified prediction method was finally established for calculating the buckling bearing capacity of those new-type retrofitted built-up steel angles. The results indicates that: no apparent difference exists in the initial stiffness for the built-up specimens compared to the unreinforced steel angles; retrofitting the steel angles by single-bolt clamps can guarantee a relatively reasonable reinforcement effect and is suggested for the reduced additional weight and higher construction efficiency; for the substructure test, the latticed substructure retrofitted by the proposed reinforcement method significantly improves the lateral stiffness, the non-deformability and energy dissipation capacity; moreover, an apparent pinching behavior exists in the hysteretic loops, and there is no obvious yield plateau in the skeleton curves; finally, the accuracy validation result indicates that the proposed theoretical model achieves a reasonable agreement with the test results. Accordingly, this study can provide valuable references for the design and application of the non-destructive upgrading project of steel angle towers.

A Study of Built-In-Test Diagnosis Mistakes as a False Alarm Filter Useful Redundant Techniques for Built-in-Test Related System

  • Oh, Hyun Seung;Yoo, Wang Jin
    • 품질경영학회지
    • /
    • 제21권2호
    • /
    • pp.1-16
    • /
    • 1993
  • Early generations of products had little to no inherent capability to test themselves. The technologies involved often required only visual inspection and limited probing to troubleshoot the system once it was turned over to maintenance personnel. However, as the complexity of military and commercial systems grew, symptoms of failure became less noticeable to the operator. Therefore, the procedure to access, inspect, repair and replace a component became complicated, the requirements for personnel skill and testing equipment increased. and it took too long of a time to maintain a system. Meanwhile, the need for availability became more mission-critical and maintenance become very expensive. The obvious solution was to design in-system circuits or devices to self-test the primary system, the Built-In-Test(BIT) was born. This approach has continued right on up through present systems and is an integral part of systems now being designed. The object of this paper is to present a state-of-the-art research for filtering out the BIT diagnosis mistakes using Bayesian analysis and develop the algorithm for Redundant systems with BIT to improve BIT diagnosis.

  • PDF

5GHz 저잡음 증폭기의 성능검사를 위한 새로운 고주파 Built-In Self-Test 회로 설계 (Design of a New RF Buit-In Self-Test Circuit for Measuring 5GHz Low Noise Amplifier Specifications)

  • 류지열;노석호;박세현
    • 한국정보통신학회논문지
    • /
    • 제8권8호
    • /
    • pp.1705-1712
    • /
    • 2004
  • 본 논문에서는 5.25GHz 저잡음 증폭기(LNA)에 대해 전압이득, 잡음지수 및 입력 임피던스를 측정할 수 있는 새로운 형태의 저가 고주파 BIST(Built-In Self-Test, 자체내부검사)회로 설계 및 검사 기술을 제안한다. 이러한 BIST 회로는 0.18$\mu\textrm{m}$ SiGe 공정으로 제작되어 있다. 이러한 접근방법은 입력 임피던스 정합과 출력 전압 측정원리를 이용한다. 본 논문에서 제안하는 방법은 측정이 간단하고 비용이 저렴하다는 장점이 있다. BIST 회로가 차지하는 면적은 LNA가 차지하는 전체면적의 약 18%에 불과하다.

5.25GHz 저잡음 증폭기를 위한 새로운 고주파 BIST 회로 설계 (Design of a New RF Built-In Self-Test Circuit for 5.25GHz SiGe Low Noise Amplifier)

  • 류지열;노석호;박세현;박세훈;이정환
    • 한국정보통신학회:학술대회논문집
    • /
    • 한국해양정보통신학회 2004년도 춘계종합학술대회
    • /
    • pp.635-641
    • /
    • 2004
  • 본 논문에서는 802.113 무선 근거리 통신망(wireless LAM)용 5.25GHz 저잡음 증폭기(LNA)에 대해 고가 장비를 사용하지 않고도 전압이득, 잡음지수 및 입력 임피던스를 측정할 수 있는 새로운 형태의 고주파 81ST(Built-In Self-Test, 자체내부검사)회로 설계 및 검사 기술을 제안한다. 본 연구에서 제작된 BIST 회로는 기존의 고가 검사 장비 대신 고주파 회로의 결함검사나 성능검사에 적용될 수 있다. 이러한 BIST 회로는 1V의 공급전압에서 동작하며, 0.18$\mu\textrm{m}$ SiGe 공정으로 제작되어 있다. 이러한 접근방법은 입력 임피던스 정합과 출력 전압 측정을 이용한다. 본 방법에서는 DUT(Device Under Test: 검사대상이 되는 소자)와 BIST 회로가 동일 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전압계와 고주파 전압 발생기만이 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다. BIST 회로가 차지하는 면적은 LNA가 차지하는 전체면적의 약 18%에 불과하다.

  • PDF

어린이 기초건축교육의 투사검사 활용 가능성에 관한 연구 - MBTI 심리선호경향과 비교분석을 통하여 - (A Study on the Possibility of Using Children's Architectural Work as Projective Test - Through Comparative Analysis with MBTI Psychological Preference Types -)

  • 이승재
    • 대한건축학회논문집:계획계
    • /
    • 제36권3호
    • /
    • pp.39-47
    • /
    • 2020
  • This study is preliminary and qualitative research to find out the possibility of using children's architectural work as projective test tools. The features of 21 works from the activity of built-environment education for children was analyzed and compared with MBTI psychological preference types. The key results are as follows: 1) Observation and communication was required to understand and analyze children's architectural works. 2) The results of children's work appeared in various ways, and were classified as indicators according to composition, shape, expression, program, circulation. These indicators also showed the independence of personal expression types regardless of age or gender. 3) The comparison between architectural expressions and MBTI preference types revealed a significant relationship between the indicators. The relationship only appeared in certain indicator pairs. Therefore, it can be said that the built-environment education could be used as a projection test tool to understand the psychological preferences of children. In conclusion, the meanings and limitations of this study and the possibility of future researches were discussed.