• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.1
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• pp.1-9
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• 2007

In this paper, a third-order harmonic mixer is designed using frequency multiplier theory for the Ka-band. The gate bias voltage is selected by frequency multiplier theory to maximize the third-order harmonic element ofthe fundamental LO frequency in the proposed mixer. The designed mixer has a gate mixer structure composed of a gate terminal input for the fundamental local signal ($f_{LO}$), RF signal (${RF}$) and a drain terminal output for the harmonic frequency ($3f_{LO}-f_{RF}$) respectively. The Ka-band harmonic mixer is designed and fabricated using a commercial GaAs MESFET device with a plastic package. The proposed mixer will provide a solution for the problems found in the high cost, complex circuitry in a conventional Ka-band mixer. The 33.5 GHz harmonic mixer has a -10 dB conversion gain by pumping 11.5 GHz LO with a +5 dBm level.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.605-608
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• 2006

The recent application of wide band gap oxide semiconductors to transparent thin film transistors (TTFTs) is making a fast and growing (r)evolution on the contemporary solid-state electronics. In this paper we present some of the recent results we have obtained using wide band gap oxide semiconductors, like indium zinc oxide, produced by rf sputtering at room temperature. The devices work in the enhancement mode and exhibit excellent saturation drain currents. On-off ratios above $10^6$ are achieved. The optical transmittance data in the visible range reveals average transmittance higher than 80 %, including the glass substrate. Channel mobilities are also quite respectable, with some devices presenting values around $25\;cm^2/Vs$, even without any annealing or other post deposition improvement processes. The high performances presented by these TTFTs associated to a high electron mobility, at least two orders of magnitude higher than that of conventional amorphous silicon TFTs and a low threshold voltage, opens new doors for applications in flexible, wearable, disposable portable electronics as well as battery-powered applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2014.11a
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• pp.108-109
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• 2014

본 논문에서는 gate와 drain bias stress하에서의 a-IGZO thin-film transistors (TFTs)의 비대칭 열화 메커니즘 분석을 진행하였다. Gate와 drain bias stress하에서의 a-IGZO TFT의 열화 현상은 conduction band edge 근처에 존재하는 oxygen vacancy-related donor-like trap의 발생으로 예상되며, TFT의 channel layer 내에서의 비대칭 열화현상은 source의 metal과 a-IGZO layer간의 contact에 전압이 인가되었을 경우, reverse-biased Schottky diode에 의한 source 쪽에서의 높은 electric field가 trap generation을 가속화시킴으로써 일어나는 것임을 확인할 수 있었다.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.60-63
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• 2003

This paper describes the design and the simulation of a V-band single pole double throw (SPDT) FET switch fur millimeter-wave applications using drain impedance transformation network with CPW transmission line. The designed switch has about 10% bandwidth at 60GHz. Insertion loss is better than 3dB fur the ON state and Isolation is larger than 30dB fer the OFF state. The maximum isolation is 43.4dB at 60GHz with input power of 10dBm. The yield analysis is done considering the effects of pHEMT variations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.2000-2006
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• 2011

In this paper, the drain induced barrier lowering(DIBL) for doping distribution in the channel has been analyzed for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing because of adventages to be able to reduce the short channel effects(SCEs) to occur in convensional MOSFET. DIBL is SCE known as reduction of threshold voltage due to variation of energy band by high drain voltage. This DIBL has been analyzed for structural parameter and variation of channel doping profile for DGMOSFET. For this object, The analytical model of Poisson equation has been derived from Gaussian doping distribution for DGMOSFET. To verify potential and DIBL models based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and DIBL for DGMOSFET has been investigated using this models.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.442-446
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased parking density. Therefore, it was interested in scaling theory, and full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot carriers in different MOSFET structures. MOSFET structures investigated in this study include a conventional MOSFET with a single source/drain, implant a lightly-doped drain(LDD) MOSFET, and a MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and those are analyzed using TCAD(Technology Computer Aided Design) for scaling and simulation. The scaling has used a constant-voltage scaling method, and we have presented MOSFET´s characteristics such as I-V characteristic, impact ionization, electric field and recognized usefulness of TCAD, providing a physical basis for understanding how they relate to scaling.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.2014-2020
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• 2017

A compact current model applicable to both single-gate (SG) and double-gate (DG) tunneling field-effect transistors (TFETs) is presented. The model is based on Kane's band-to-band tunneling (BTBT) model. In this model, the well-known and previously-reported quasi-2-D solution of Poisson's equation is used for the surface potential and length of the tunneling path in the tunneling region. An analytical tunneling current expression is derived from expressions of derivatives of local electric field and surface potential with respect to tunneling direction. The previously reported correction factor with three fitting parameters, compensating for superlinear onset and saturation current with drain voltage, is used. Simulation results of the proposed TFET model are compared with those from a technology computer-aided-design (TCAD) simulator, and good agreement in all operational bias is demonstrated. The proposed SG/DG-TFET model is developed with Verilog-A for circuit simulation. A TFET inverter is simulated with the Verilog-A SG/DG-TFET model in the circuit simulator; the model exhibits typical inverter characteristics, thereby confirming its effectiveness.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.6
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• pp.540-545
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• 2015

This paper presents the design, fabrication and measurement results of a S-band internally-matched power amplifier using Gallium Nitride High Electron Mobility Transistor(GaN HEMT) die. In order to fabricate the S-band internally-matched power amplifier, a high dielectric substrate and alumina were used for input/output matching circuits. The measured output power is 55.4 dBm, the drain efficiency is 78 % and the power gain is 11 dB under pulse operation at the frequency of 3 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.4 s.95
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• pp.345-350
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• 2005

An X-band push-push VCO for low cost applications is proposed. The designed push-push oscillator achieves a wide tuning range in the X-band by the collector bias tuning instead of extra varactor diodes. The measurement shows a wide tuning bandwidth of $900\;\cal{MHz}\;from\;10.9\;\cal{GHz}\;to\;11.8\;\cal{GHz}$ with a drain bias voltage varying from 4 to 9 V, excellent fudamental suppression of $-30\;\cal{dBc}$ and good phase noise of $-115\;\cal{dBc/Hz}\;@\;1\;\cal{MHz}$ offset.