• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.829-838
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• 2016

This paper focuses on the engineering trade-offs in designing capacitor voltage balancing schemes for modular multilevel converters (MMC) HVDC: regulation performance and switching loss. MMC is driven by the on/off switch operation of numerous submodules and the key design concern is balancing submodule capacitor voltages minimizing switching transition among submodules because it represents the voltage regulation performance and system loss. This paper first introduces the state-of-the-art MMC-HVDC submodule capacitor voltage balancing methods reported in the literatures and discusses the trade-offs in designing these methods for HVDC application. This paper further proposes a submodule capacitor balancing scheme exploiting a control signal to flexibly interchange between the on-state and the off-state submodules. The proposed scheme enables desired performance-based voltage regulation and avoids unnecessary switching transitions among submodules, consequently reducing the switching loss. The flexibility and controllability particularly fit in high-level MMC HVDC applications where the aforementioned design trade-offs become more crucial. Simulation studies for MMC HVDC are performed to demonstrate the validity and effectiveness of the proposed capacitor voltage balancing algorithm.

• Journal of Power Electronics
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• v.17 no.3
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• pp.653-663
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• 2017

Multilevel active neutral-point-clamped (ANPC) converter combines the advantages of three-level ANPC converter and multilevel flying capacitor (FC) converter. However, multilevel ANPC converter often suffers from capacitor voltage balancing problems. In order to solve the capacitor voltage balancing problems for five-level ANPC converter, phase-shifted pulse width modulation (PS-PWM) is used, which generally provides natural voltage balancing ability. However, the natural voltage balancing ability depends on the load conditions and converter parameters. In order to eliminate voltage deviations under steady-state and dynamic conditions, the active voltage-balancing control (AVBC) methods of floating capacitors and dc-link capacitors based on PS-PWM are proposed. First, the neutral-point current is regulated to balance the neutral-point voltage by injecting zero-sequence voltage. After that, the duty cycles of the redundant switch combinations are adjusted to balance the floating-capacitor voltages by introducing moderating variables for each of the phases. Finally, the effectiveness of the proposed AVBC methods is verified by experimental results.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.298-301
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• 2005

The flying capacitor voltage control of the flying capacitor multi-level inverter (FCMLI) is very important for safe operation. The voltage unbalancing of flying capacitors caused serious problems in safety and reliability of system. In the FCMLI, balancing problem of the flying capacitor has its applications limited. The voltage unbalance is occurred by the difference of each capacitors charging and discharging time applied to FCMLI. This paper investigates and analyzes multi-carrier PWM methods to solve capacitor voltage balancing problem. The Phase-Shift PWM (PSPWM) method that is commonly used, The Modified Carrier-Redistribution PWM (MCRPWM) method and The Saw-Tooth-Rotation PWM (STRPWM) method are discussed and compared with respect to switching state, balancing voltage of capacitors and output waveform. These three PWM methods are analyzed by using a flying capacitor three-level inverter and provided result through simulation. Finally, the harmonics about the output voltages of their methods are compared using the harmonic distortion factor (HDF).

• Journal of Power Electronics
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• v.15 no.3
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• pp.660-669
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• 2015

This paper presents a control scheme with a focus on the combination of phase disposition pulse width modulation (PDPWM) and DC capacitor voltage control for a chopper-cell based modular multilevel converter (MMC) for the purpose of eliminating the time-consuming voltage sorting algorithm and complex voltage balancing regulators. In this paper, the convergence of the DC capacitor voltages within one arm is realized by charging the minimum voltage module and discharging the maximum voltage module during each switching cycle with the assistances of MAX/MIN capacitor voltage detection and PDPWM signals exchanging. The process of voltage balancing control introduces no extra switching commutation, which is helpful in reducing power loss and improving system efficiency. Additionally, the proposed control scheme also possess the merit of a simple executing procedure in application. Simulation and experimental results indicates that the MMC circuit together with the proposed method functions very well in balancing the DC capacitor voltage and improving system efficiency even under transient states.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.209-215
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• 2018

This paper present a 7-level PWM inverter adopting voltage balancing control to series-connected input capacitors. The prior proposed 7-level PWM inverter consists of dc input source, three series-connected capacitors, two bidirectional switch modules, and an H-bridge. This circuit topology is useful to increase the number of output voltage levels, however it fails to generate 7-level in output voltage without consideration for voltage balancing among series-connected capacitors. Capacitor voltage imbalance is caused on the different period between charging and discharging of capacitor. To solve this problem, we uses the amplitude modulation of carrier wave, which is used to produce the center output voltage level. To verify the validity of the proposed control method, we carried out computer-aided simulation and experiments using a prototype.

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2227-2236
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• 2017

In order to solve the neutral-point voltage fluctuation problem of three-phase three-level T-type inverters (TPTLTIs), the unbalance characteristics of capacitor voltages under different switching states and the mechanism of neutral-point voltage fluctuation are revealed. Based on the mathematical model of a TPTLTI, a feed-forward voltage balancing control strategy of DC-link capacitor voltages error is proposed. The strategy generates a DC bias voltage using a capacitor voltage loop with a proportional integral (PI) controller. The proposed strategy can suppress the neutral-point voltage fluctuation effectively and improve the quality of output currents. The correctness of the theoretical analysis is verified through simulations. An experimental prototype of a TPTLTI based on Digital Signal Processor (DSP) is built. The feasibility and effectiveness of the proposed strategy is verified through experiment. The results from simulations and experiment match very well.

• Journal of Power Electronics
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• v.18 no.2
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• pp.432-444
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• 2018

This paper presents a capacitor voltage balancing topology using a three-level boost converter (TLBC) for a neutral point clamped (NPC) three-level inverter fed surface permanent magnet synchronous motor drive (SPMSM). It enhanced the performance of the drive in terms of its voltage THD and torque pulsation. The main attracting feature of the proposed control is the boosting of the input voltage and at the same time the balancing of the capacitor voltages. This control also reduces the computational complexity. For the purpose of close loop vector control, a software based cost effective resolver to digital converter RDC-less estimation is implemented to calculate the speed and position. The proposed drive is simulated in the MATLAB/SIMULINK environment and an experimental investigation using dSPACE DS1104 validates the proposed drive system at different operating condition.

• Journal of Power Electronics
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• v.14 no.2
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• pp.282-291
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• 2014

This paper presents a detailed theoretical analysis and performance assessment of the capacitor voltage balancing strategies for staircase modulated modular multilevel converters (MMC) in terms of the algorithm structures, voltage balancing effect, and switching frequency. A constant-frequency redundancy selection (CFRS) method with minimal switching loss is proposed and the function realization of specific modules of the algorithm is given. This method is simple and efficient in both switching frequency and regulation capacity. Laboratory results show very good agreement with the theoretical analysis and numerical simulations.

• Journal of Power Electronics
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• v.17 no.1
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• pp.96-105
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• 2017

In this paper, a hybrid modular multilevel converter (MMC) topology with an improved nearest level modulation method is proposed for medium-voltage high-power applications. The arm of the proposed topology contains N series connected half-bridge submodules (HBSMs), one full-bridge submodule (FBSM) and an inductor. By exploiting the FBSM, half-level voltages are obtained in the arm voltages. Therefore, an output voltage with a 2N+1 level number can be generated. Moreover, the total level number of the inserted submodules (SMs) is a constant. Thus, there is no pulse voltage across the arm inductors, and the SM capacitor voltage is rated. With the proposed voltage balancing method, the capacitor voltage of the HBSM is twice the voltage of the FBSM, and each IGBT of the FBSM has a relatively low switching frequency and an equalized conduction loss. The capacitor voltage balancing methods of the two kinds of SMs are implemented independently. As a result, the switching frequency of the HBSM is not increased compared to the conventional MMC. In addition, according to a theoretical calculation of the total harmonic distortion of the electromotive force (EMF), the voltage quality with the presented method can be significantly enhanced when the SM number is relatively small. Simulation and experimental results obtained with a MMC-based inverter verify the validity of the developed method.

• Journal of Power Electronics
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• v.17 no.1
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• pp.115-126
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• 2017

This paper presents a new cascaded asymmetrical single phase multilevel converter with a reduced number of isolated DC sources and power semiconductor switches. The proposed inverter has only two H-bridges connected in cascade, one switching at a high frequency and the other switching at a low frequency. The Low Switching Frequency Inverter (LSFI) generates seven levels whereas the High Switching Frequency Inverter (HSFI) generates only two levels. This paper also presents a solution to the capacitor balancing issues of the LSFI. The proposed inverter has lot of advantages such as reductions in the number of DC sources, switching losses, power electronic devices, size and cost. The proposed inverter with a capacitor voltage balancing algorithm is simulated using MATLAB/SIMULINK. The switching logic of the proposed inverter with a capacitor voltage balancing algorithm is developed using a FPGA SPATRAN 3A DSP board. A laboratory prototype is built to validate the simulation results.