• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.49-55
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• 2015

The inaccuracy of the bias-dependent gate-drain overlap capacitance $C_{gdo}$ simulation in original BSIM4 and BSIM4 macro model using a diode is analyzed in detail. It is found that the accuracy of the macro model is better than of the BSIM4. However, the macro model cannot be used in the linear region. In order to remove the inaccuracy of the conventional models, a new BSIM4 macro model with a physical bias-dependent $C_{gdo}$ equation is proposed and its accuracy is validated in the full bias range.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.173-178
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• 2012

Using accurate MOSFET substrate parameters obtained by a RF direct extraction method, it is demonstrated that a BSIM4 model with only substrate resistances is not physically valid to apply in the wide range of gate length because of scaling inaccuracy. In order to remove the unphysical problem of the BSIM4, a modified BSIM4 model with additional dielectric substrate capacitance is used and its physical validity is verified by observing excellent gate length scalability.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.613-614
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• 2006

In this paper, BSIM4's IIR(Intrinsic Input Resistance) model that has a difficulty to predict $Z_{11}$ exactly is investigated by analyzing S-parameter measurement. Then a BSIM4 macro model for 70nm RF MOSFETs is proposed. That model uses external effective gate resistance which is composed of R and parallel RC. Comparison between simulation results using proposed model and IIR model is shown. The proposed model shows a better agreement between measured and simulated results up to 20GHz.

• Investigative Magnetic Resonance Imaging
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• v.19 no.3
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• pp.168-177
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• 2015

Purpose: Brain surface intensity model (BSIM)-based cortical thickness analysis does not require complicated 3D segmentation of brain gray/white matters. Instead, this technique uses the local intensity profile to compute cortical thickness. The aim of the present study was to evaluate intra-rater and inter-rater reliability of BSIM-based cortical thickness analysis using images from elderly participants. Materials and Methods: Fifteen healthy elderly participants (ages, 55-84 years) were included in this study. High-resolution 3D T1-spoiled gradient recalled-echo (SPGR) images were obtained using 3T MRI. BSIM-based processing steps included an inhomogeneity correction, intensity normalization, skull stripping, atlas registration, extraction of intensity profiles, and calculation of cortical thickness. Processing steps were automatic, with the exception of semiautomatic skull stripping. Individual cortical thicknesses were compared to a database indicating mean cortical thickness of healthy adults, in order to produce Z-score thinning maps. Intra-class correlation coefficients (ICCs) were calculated in order to evaluate inter-rater and intra-rater reliabilities. Results: ICCs for intra-rater reliability were excellent, ranging from 0.751-0.940 in brain regions except the right occipital, left anterior cingulate, and left and right cerebellum (ICCs = 0.65-0.741). Although ICCs for inter-rater reliability were fair to excellent in most regions, poor inter-rater correlations were observed for the cingulate and occipital regions. Processing time, including manual skull stripping, was $17.07{\pm}3.43min$. Z-score maps for all participants indicated that cortical thicknesses were not significantly different from those in the comparison databases of healthy adults. Conclusion: BSIM-based cortical thickness measurements provide acceptable intra-rater and inter-rater reliability. We therefore suggest BSIM-based cortical thickness analysis as an adjunct clinical tool to detect cortical atrophy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.7-12
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• 2008

In this study, the wide width effect that the increasing rate of drain current and the value of cutoff frequency decrease with larger finger number is observed. For modeling this effect, an improved SPICE MOSFET RF model that finger number-independent external source resistance is connected to a conventional BSIM3v3 RF model is developed. Better agreement between simulated and measured drain current and cutoff frequency at different finger number is obtained for the improved model than the conventional one, verifying the accuracy of the improved model for $0.13{\mu}m$ multi-finger MOSFET.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.671-674
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• 2005

The series parasitic resistances ($R_s$, $R_g$, $R_d$, $R_{sub}$) of BSIM3v3 RF MOSFET macro model were directly extracted from measured S-parameters in the GHz region by using simple 2-port parameter equations. Also, overlap capacitance and junction capacitance parameters were extracted by tuning $S_{11}$, $S_{12}$, and $S_{22}$ respectively while DC-parameters and all parasitic resistances are fixed at previously extracted values. These data are verified to be accurate by observing good correspondence between modeled and measured S-parameters up to 10GHz.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.675-678
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• 2005

An improved BSIM3v3 RF Macro model with RC parallel substrate circuit has been developed to simulate RF characteristics of the output admittance in MOSFET accurately. This improved model shows better agreements with measured $Y_{22}-parameter$ up to 10 GHz than conventional one with a single substrate resistance, verifying the accuracy of the improved one.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.485-489
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• 2015

An accurate large-signal BSIM4 macro model including new empirical bias-dependent equations of the drain-source capacitance and channel resistance constructed from bias-dependent data extracted from S-parameters of RF MOSFETs is developed to reduce $S_{22}$-parameter error of a conventional BSIM4 model. Its accuracy is validated by finding the much better agreement up to 40 GHz between the measured and modeled $S_{22}$-parameter than the conventional one in the wide bias range.

• Journal of the Semiconductor & Display Technology
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• v.19 no.1
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• pp.61-66
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• 2020

Threshold voltage shift occurring during operation is implemented in a SPICE simulation tool. Among the shift models the stretched-exponential function model, which is frequently observed from both single-crystal silicon and thin-film transistors regardless of the nature of causes, is selected, adapted to transient simulation, and added to BSIM4 developed by BSIM Research Group at the University of California, Berkeley. The adaptation method used in this research is to select degradation and recovery models based on the comparison between the gate and threshold voltages. The threshold voltage shift is extracted from SPICE transient simulation and shows the stretched-exponential time dependence for both degradation and recovery situations. The implementation method developed in this research is not limited to the stretched-exponential function model and BSIM model. The proposed method enables to perform transient simulation with threshold voltage shift in situ and will help to verify the reliability of a circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.