Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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70nm CMOS BSIM4 Macro modeling for RFIC design

RFIC설계를 위한 70nm CMOS의 BSIM4 매크로 모델링

  • Choi, Gil-Bok (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Baek, Rock-Hyun (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Kang, Hee-Sung (System LSI Division, Samsung Electronics Co., Ltd.) ;
  • Jeong, Yoon-Ha (Department of Electronic and Electrical Engineering Pohang University of Science and Technology)
  • 최길복 (포항공과대학교 전자전기공학과) ;
  • 백록현 (포항공과대학교 전자전기공학과) ;
  • 강희성 ;
  • 정윤하 (포항공과대학교 전자전기공학과)
  • Published : 2006.06.21
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Abstract

In this paper, BSIM4's IIR(Intrinsic Input Resistance) model that has a difficulty to predict $Z_{11}$ exactly is investigated by analyzing S-parameter measurement. Then a BSIM4 macro model for 70nm RF MOSFETs is proposed. That model uses external effective gate resistance which is composed of R and parallel RC. Comparison between simulation results using proposed model and IIR model is shown. The proposed model shows a better agreement between measured and simulated results up to 20GHz.

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