• ETRI Journal
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• v.36 no.6
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• pp.894-904
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• 2014

Blind mismatch correction of time-interleaved analog-to-digital converters (TI-ADC) is a challenging task. We present a practical blind calibration technique for low-computation, low-complexity, and high-resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI-ADC channels and most real-life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed-domain error correction. The proposed technique is experimentally verified by an M = 4 400 MSPS TI-ADC system. In a single-tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.6
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• pp.220-223
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• 2003

In this paper, a new frequency-to-digital converter without an analog element is proposed. The proposed circuit consists of pulse-shrinking elements, latches and D flip-flops, and the operation is based on frequency comparison by the pulse-shrinking element. In the proposed circuit, the resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements. The FDC performance is improved in viewpoints of operating speed and chip area. In designed FDC, error of frequency-to-digital conversion is less than 0.1 %.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.361-364
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• 2003

In this paper, a high-resolution multibit sigma-delta modulator implemented in a.0.35-um CMOS technology is introduced. This modulator consists of two switched capacitor integrators, 3-bits A/D converter, and 3-bits D/A converter For the verification of the internal function blocks, HSPICE simulator is used. This circuit is normally operated at 130 MHz clock and the total power dissapation is 70 mW.

• Analytical Science and Technology
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• v.5 no.3
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• pp.295-301
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• 1992

A versatile data acquisition and control adaptor for IBM personal computers has been developed. The data acquisition and control adaptor developed contains major components necessary for computerized data acquisition and control instrumentaions. Up to 4 differential analog signals can be acquired through a choice of dual 12-bit analog-to digital converters depending on the experimental requirements. Also, dual 12-bit digital-to-analog converters, three 16-bit programmable most computerized laboratory data acquisition and control instrumentation. The design principle and its applications are described.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1019-1024
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• 2007

In this paper, the 10bit 20MHz pipelined analog-to-digital converter that is able to apply to WLAN system was modeled for ADC design. Each blocks in converter such as sample and hold amplifier(SHA), comparator, multiplyng DAC(MDAC), and digital correction logic(DCL) was modeled. The pipelined ADC with these modeled blocks takes 1/50 less time than the one of simulation using HSPICE.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.137-140
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• 2002

This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.301-304
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• 2002

This paper has been studied an A/D conversion system for precision weighing signal process In weighing system. A/D conversion has some problem.; offset drift voltage with environment situation and nonzero value of initial output voltage. The Offset voltage in analog circuit produces a drift of an output voltage before A/D conversion stage. This paper suggested the method of reducing the offset voltage by switching analog chopping circuit and making the initial output close to zero to enhance the swing range by D/A converter. Also, we have designed active filter and digital filter with Auto Zero Tracking algorithm for better signal process of the weighing system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.230-238
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• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.