Browse > Article
http://dx.doi.org/10.4218/etrij.14.0114.0110

Mixed-Domain Adaptive Blind Correction of High-Resolution Time-Interleaved ADCs  

Seo, Munkyo (College of Information and Communication Engineering, Sungkyunkwan University)
Nam, Eunsoo (Components & Materials Research Laboratory, ETRI)
Rodwell, Mark (Department of Electrical and Computer Engineering, University of California)
Publication Information
ETRI Journal / v.36, no.6, 2014 , pp. 894-904 More about this Journal
Abstract
Blind mismatch correction of time-interleaved analog-to-digital converters (TI-ADC) is a challenging task. We present a practical blind calibration technique for low-computation, low-complexity, and high-resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI-ADC channels and most real-life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed-domain error correction. The proposed technique is experimentally verified by an M = 4 400 MSPS TI-ADC system. In a single-tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique.
Keywords
Analog-to-digital conversion; mismatch; blind algorithm; adaptive technique;
Citations & Related Records
연도 인용수 순위
  • Reference
1 W.C. Black and D.A. Hodges, "Time Interleaved Converter Arrays," IEEE J. Solid-State Circuits, vol. 15, no. 6, Dec. 1980, pp. 1022-1029.   DOI
2 K. Poulton et al., "A 20 GS/s 8 b ADC with a 1 MB Memory in 0.18 ${\mu}m$ CMOS," IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, Feb. 13, 2003, pp. 318-496.
3 A. Petraglia and S.K. Mitra, "Analysis of Mismatch Effects among A/D Converters in a Time-Interleaved Waveform Digitizer," IEEE Trans. Instrum. Meas., vol. 40, no. 5, Oct. 1991, pp. 831-835.   DOI   ScienceOn
4 N. Kurosawa et al., "Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, Mar. 2001, pp. 261-271.   DOI   ScienceOn
5 C. Vogel and H. Johansson, "Time-Interleaved Analog-to-Digital Converters: Status and Future Directions," IEEE Int. Symp. Circuits Syst., Kos Island, Greece, May 21-24, 2006, pp. 3386-3389.
6 M. Seo, M. Rodwell, and U. Madhow, "Comprehensive Digital Correction of Mismatch Errors for a 400-Msamples/s, 80-db SFDR Time-Interleaved Analog-to-Digital Converter," IEEE Trans. Microw. Theory Techn., vol. 53, no. 3, Mar. 2005, pp. 1072-1082.   DOI   ScienceOn
7 S.M. Jamal et al., "A 10-b 120-Msample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration," IEEE J. Solid-State Circuits, vol. 37, no. 12, Dec. 2002, pp. 1618-1627.   DOI   ScienceOn
8 S.M. Jamal et al., "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, Jan. 2004, pp. 130-139.   DOI
9 J. Matsuno et al., "All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 5, May 2013, pp. 1113-1121.   DOI   ScienceOn
10 V. Divi and G. Wornell, "Blind Calibration of Timing Skew in Time-Interleaved Analog-to-Digital Converters," IEEE J. Sel. Topics Signal Process., vol. 3, no. 3, June 2009, pp. 509-522.   DOI   ScienceOn
11 J. Elbornsson, F. Gustafsson, and J.-E. Eklund, "Blind Adaptive Equalization of Mismatch Errors in a Time-Interleaved A/D Converter System," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, Jan. 2004, pp. 151-158.   DOI
12 S. Saleem and C. Vogel, "Adaptive Blind Background Calibration of Polynomial-Represented Frequency Response Mismatches in a Two-Channel Time-Interleaved ADC," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 6, June 2011, pp. 1300-1310.   DOI   ScienceOn
13 C. Law, P. Hurst, and S. Lewis, "A Four-Channel Time-Interleaved ADC with Digital Calibration of Interchannel Timing and Memory Errors," IEEE J. Solid-State Circuits, vol. 45, no. 10, Oct. 2010, pp. 2091-2103.   DOI   ScienceOn
14 S. Huang and B.C. Levy, "Adaptive Blind Calibration of Timing Offset and Gain Mismatch for Two-Channel Time-Interleaved ADCs Converters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 6, June 2006, pp. 1278-1288.   DOI   ScienceOn
15 S. Huang and B.C. Levy, "Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 4, Apr. 2007, pp. 863-876.   DOI   ScienceOn
16 M. Seo, M. Rodwell, and U. Madhow, "Blind Correction of Gain and Timing Mismatches for a Two-Channel Time-Interleaved Analog-to-Digital Converter," Asilomar Conf. Signals, Syst. Comput., Pacific Grove, CA, USA, Oct. 2005, pp. 1121-1125.
17 M. Seo, M. Rodwell, and U. Madhow, "Blind Correction of Gain and Timing Mismatches for a Two-Channel Time-Interleaved Analog-to-Digital Converter: Experimental Verification," IEEE Int. Symp. Circuits Syst., Kos Island, Greece, May 21-24, 2006, pp. 3394-3397.
18 H. Jin and E.K.F. Lee, "A Digital-Background Calibration Technique for Minimizing Timing-Error Effects in Time-Interleaved ADCs," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 7, July 2000, pp. 603-613.   DOI   ScienceOn
19 D. Fu et al., "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. Solid-State Circuits, vol. 33, no. 12, Dec. 1998, pp. 1904-1911.   DOI   ScienceOn
20 K.C. Dyer et al., "An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. Solid-State Circuits, vol. 33, no. 12, Dec. 1998, pp. 1912-1919.   DOI   ScienceOn
21 E. Iroaga, B. Murmann, and L. Nathawad, "A Background Correction Technique for Timing Errors in Time-Interleaved Analog-to-Digital Converters," IEEE Int. Symp. Circuits Syst., Kobe, Japan, vol. 6, May 23-26, 2005, pp. 5557-5560.
22 C.-C. Huang, C.-Y. Wang, and J.-T. Wu, "A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques," IEEE J. Solid-State Circuits, vol. 46, no. 4, Apr. 2011, pp. 848-858.   DOI   ScienceOn
23 D. Camarero et al., "Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, Dec. 2008, pp. 3676-3687.   DOI   ScienceOn
24 A. Haftbaradaran and K. Martin, "A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 3, Mar. 2008, pp. 234-238.   DOI   ScienceOn
25 M. El-Chammas and B. Murmann, "A 12-GS/s 81-mW 5-Bit Time-Interleaved Flash ADC with Background Timing Skew Calibration," IEEE J. Solid-State Circuits, vol. 46, no. 4, Apr. 2011, pp. 838-847.   DOI   ScienceOn
26 M. Seo, M. Rodwell, and U. Madhow, "A Low Computation Adaptive Blind Correction for Time-Interleaved ADCs," IEEE Int. Midwest Symp. Circuits Syst., San Juan, Puerto Rico, Aug. 6-9, 2006, pp. 292-296. 904