[KSCI] Korea Science Citation Index Service

Modeling of Pipeline A/D converter with Verilog-A

Park, Sang-Wook (삼성전자 시스템 LSI 사업부)
Lee, Jae-Yong (인하대학교 전자공학과)
Yoon, Kwang-Sub (인하대학교 전자공학과)

Publication Information

The Journal of Korean Institute of Communications and Information Sciences / v.32, no.10C, 2007 , pp. 1019-1024 More about this Journal

Abstract

In this paper, the 10bit 20MHz pipelined analog-to-digital converter that is able to apply to WLAN system was modeled for ADC design. Each blocks in converter such as sample and hold amplifier(SHA), comparator, multiplyng DAC(MDAC), and digital correction logic(DCL) was modeled. The pipelined ADC with these modeled blocks takes 1/50 less time than the one of simulation using HSPICE.

Keywords

ADC(Analog-to-Digital Converter); Pipeline; Top-down; Modeling; Verilog-A;

Citations & Related Records

Reference

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KSCI

Modeling of Pipeline A/D converter with Verilog-A Verilog-A를 이용한 파이프라인 A/D변환기의 모델링

Modeling of Pipeline A/D converter with Verilog-A