The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Modeling of Pipeline A/D converter with Verilog-A

Verilog-A를 이용한 파이프라인 A/D변환기의 모델링

  • 박상욱 (삼성전자 시스템 LSI 사업부) ;
  • 이재용 (인하대학교 전자공학과) ;
  • 윤광섭 (인하대학교 전자공학과)
  • Published : 2007.10.31
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Abstract

In this paper, the 10bit 20MHz pipelined analog-to-digital converter that is able to apply to WLAN system was modeled for ADC design. Each blocks in converter such as sample and hold amplifier(SHA), comparator, multiplyng DAC(MDAC), and digital correction logic(DCL) was modeled. The pipelined ADC with these modeled blocks takes 1/50 less time than the one of simulation using HSPICE.

본 논문에서는 무선 랜 시스템용 10비트 20MHz 파이프라인 아날로그-디지털 변환기 설계를 위해서 Verilog-A 언어를 사용하여서 모델링하였다. 변환기내 샘플 / 홀드 증폭기, 비교기, MDAC 및 오차 보정 회로 등의 구성회로들을 각각 모델링해서 모의실험 한 결과 HSPICE를 이용한 모의 실험 시간보다 1/50배로 단축되어서 시스템 모델링에 적합함을 확인하였다.

Keywords

References

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