Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2003.11c
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- Pages.361-364
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- 2003
The Design of a high resolution 2-order Sigma-Delta modulator
고해상도 2차 Sigma-Delta 변조기의 설계
Abstract
In this paper, a high-resolution multibit sigma-delta modulator implemented in a.0.35-um CMOS technology is introduced. This modulator consists of two switched capacitor integrators, 3-bits A/D converter, and 3-bits D/A converter For the verification of the internal function blocks, HSPICE simulator is used. This circuit is normally operated at 130 MHz clock and the total power dissapation is 70 mW.
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