• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.05a
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• pp.341-344
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• 2003

There communicates using tire supersonic waves in tire underwater, that is different from tire ground that use tire propagation. Because using Law frequency to come under tire waves, bandwidth that is able to communicate is very smaller that tire mobile communication of tire ground. Also, The channel environment changes rapidly in tire shallow underwater than tire ground. Due to such a reason, data transmission technic that is able to tire maximum application to restricted bandwidth and tire signal processing technics that is able to conquer tire rapid changes of tire channel environment are being used. Algorithm is used at tire application of these technic has a lot of tire calculating quantity. So this research reveals small bulk and equal performance using one DSP chip and then implements QPSK transmitter, that uses SHARC DSP of Analog Device company, for tire underwater supersonic waves communication rapidly decrease tire calculating quantity.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1108-1110
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• 1995

This paper presents a balanced CMOS complementary folded cascode OP-AMP topology that achieves improved DC gain using the gain boosting technique, a high unity-gain frequency and improved slew rate using the CMOS complementary cascode structure and a high PSRR using the balanced output stage. Bode-plot measurements of a balanced CMOS complementary folded cascode OP-AMP show a DC gain of 80dB, a unity-gain frequency of 110MHz and a slew rate of $274V/{\mu}s$(1pF load). This balanced CMOS complementary folded cascode OP-AMP is well suited for high frequency analog signal processing applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.249-256
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• 2009

As a wireless handset deals with multiple application standards concurrently, RF transmitters and power amplifiers are required to be more power efficient and reconfigurable. In this paper, we review the recent advances in the design of the power amplifiers and transmitters. Then, the systematic design approaches to improve the performance with the digital baseband signal processing are introduced for the next generation mobile handset.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.145-148
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• 2015

In this letter, we present a new linearization method for a voltage controlled oscillator (VCO)-based quantizer in an analog-to-digital converter (ADC). The nonlinearity of the VCO generates unwanted harmonic spurs and reduces the signal-to-noise and distortion ratio (SNDR) of the VCO-based quantizer. This letter suggests a frequency-to-current feedback method to effectively suppress harmonic distortion. The proposed method decreases the harmonic spurs by more than 53 dB. And a VCO-based quantizer employing the proposed linearization method achieves a high SNDR of 74.1 dB.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.951-954
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• 2001

본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1406-1409
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• 2004

The Resolver usually used in industry is the absolute angle analog sensor that must be in order to driving BLDC (brushless DC) motor, and it needs RDC(Resolver-to-Digital converter) for changing the output signal to digital to be applied to the SVPWM(Space Vector Pulse Width Modulation) algorithm. Commonly used S/W RDC needs trigonometric function. What it takes a lot of calculation time of processor is gotten at weak point. In this paper, S/W RDC is realized except trigonometric functions as a result of feedback resolver outputs after filtering using FIR filter. thus, processing time is reduced. So, One-chip DSP Controller operating the Vector Control, RDC, and SVPWM can be designed.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1250-1254
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• 1992

This paper describes the designed and fabricated thermal imaging system with the SPRITE(Signal PRocessing in The Element) detector, operating in the 3-12 micron band. This system consists of an afocal telescope, a scan unit containing the SPRITE detector, an electronic processor unit and a cooler. The optical scan system utilizing rotating polygon and oscillating mirror, is 2-dimensional serial/parallel scan type using five elements of the detector. And the electronic processor unit performs digital scan conversion to reform the parallel data stream into serial analog data compatable with conventional RS-170 video. The scan field of view is 40 ${\times}$ 26.7 and the MRTD(Minium Resolvable Temperature Difference) is 0.6 K at 7.5 cycles/mm. The acquired thermal image indicates that this system has a satisfactory performance.

• Journal of Astronomy and Space Sciences
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• v.12 no.1
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• pp.54-65
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• 1995

We present a design study for a remote sensing camera system which can be operated in multi-channel mode simultaneously with several bandpass filters. The camera control electronics is based on the multiplexed driving concept, which can provide a variety of flexibility for system control parameters and its individual optimisation. The design can also be applied to any system with linear sensors or frame sensors according to its functional requirements. The system design parameters have been examined, including modification of driving waveforms for different types of sensors, waveforms for low-nosie readout circuit in analog chain, and synchronisation with other signal processing.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.190-195
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• 2005

The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.