• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제23권6호
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• pp.706-715
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• 2012

Electro-optical sigma-delta modulators are the core module of digital receiver to digitize wideband radio-frequency signals directly at an antenna. Electro-optical sigma-delta modulators use a pulsed laser to oversample an input radio-frequency signals at two Mach-Zehnder Interferometer(MZI) and shape the quantization noise using a fiber-lattice accumulator. Decimation filtering is applied to the quantizer output to construct the input signal with high resolution. The jitter affects greatly on reconstructing the original input signal of modulator. This paper analyzes the performance of first order single bit electro-optical sigma-delta modulator in the time domain and the frequency domain. The performance of modulator is analyzed by using asynchronous spectral averaging of the reconstructed signal's spectrum in the frequency domain. The reference value of time jitter is presented by analyzing the performance of jitter effects. This kind of jitter value can be used as a reference value on the design of modulators.

• Journal of the Institute of Electronics and Information Engineers
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• 제50권9호
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제43권12호
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• pp.15-22
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• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제44권11호
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• pp.74-81
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• 2007

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제43권11호
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제34권11C호
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• pp.1085-1097
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• 2009

We present a structure and design method of the D8PSK modem compatible with the VDL mode-2 standard and performance test results of the developed modem. In VDL mode-2, the raised cosine filter is used only in the transmitter and a general low pass filter is used in the receiver. Consequently, we can not achieve ISI reduction but can have better spectrum characteristics. Although there is 1~2 dB performance degradation with an un-matched filter compared to that with a matched filter, it is more important to minimize adjacent channel interference in narrow band communications. The transmit signal is generated digitally to avoid the problems(I/Q imbalance and DC offset etc.) of analog modulators. In addition the digital down converter using digital IF sampling technique is adopted for the receiver. This paper contains the overall configuration, design method and simulation results based in part on the previously proposed structures and algorithms. It is confirmed that the modem transmits and receives messages successfully at a speed of max. 870 km/h over ranges of up to 310 km through the ground and in-flight communication tests.

• Investigative Magnetic Resonance Imaging
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• 제8권1호
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• pp.42-49
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• 2004

Purpose : The quantization noise in magnetic resonance imaging (MRI) systems is analyzed. The signal-to-quantization noise ratio (SQNR) in the reconstructed image is derived from the level of quantization in the signal in spatial frequency domain. Based on the derived formula, the SQNRs in various main magnetic fields with different receiver systems are evaluated. From the evaluation, the quantization noise could be a major noise source determining overall system signal-to-noise ratio (SNR) in high field MRI system. A few methods to reduce the quantization noise are suggested. Materials and methods : In Fourier imaging methods, spin density distribution is encoded by phase and frequency encoding gradients in such a way that it becomes a distribution in the spatial frequency domain. Thus the quantization noise in the spatial frequency domain is expressed in terms of the SQNR in the reconstructed image. The validity of the derived formula is confirmed by experiments and computer simulation. Results : Using the derived formula, the SQNRs in various main magnetic fields with various receiver systems are evaluated. Since the quantization noise is proportional to the signal amplitude, yet it cannot be reduced by simple signal averaging, it could be a serious problem in high field imaging. In many receiver systems employing analog-to-digital converters (ADC) of 16 bits/sample, the quantization noise could be a major noise source limiting overall system SNR, especially in a high field imaging. Conclusion : The field strength of MRI system keeps going higher for functional imaging and spectroscopy. In high field MRI system, signal amplitude becomes larger with more susceptibility effect and wider spectral separation. Since the quantization noise is proportional to the signal amplitude, if the conversion bits of the ADCs in the receiver system are not large enough, the increase of signal amplitude may not be fully utilized for the SNR enhancement due to the increase of the quantization noise. Evaluation of the SQNR for various systems using the formula shows that the quantization noise could be a major noise source limiting overall system SNR, especially in three dimensional imaging in a high field imaging. Oversampling and off-center sampling would be an alternative solution to reduce the quantization noise without replacement of the receiver system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제43권12호
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• 제38권3호
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• pp.249-255
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• 2002

This paper describes on the extraction of ship's real-time movement information using a combination full-function ARPA radar and ECS system that displays radar images and an electronic chart together on a single PC screen. The radar target extractor(RTX) board, developed by Marine Electronics Corporation of Korea, receives radar video, trigger, antenna bearing pulse and heading pulse signals from a radar unit and processes these signals to extract target information. The target data extracted from each pulse repetition interval in DSPs of RTX that installed in 16 bit ISA slot of a IBM PC compatible computer is formatted into a series of radar target messages. These messages are then transmitted to the host PC and displayed on a single screen. The position data of target in range and azimuth direction are stored and used for determining the center of the distributed target by arithmetic averaging after the detection of the target end. In this system, the electronic chart or radar screens can be displayed separately or simulaneously and in radar mode all information of radar targets can be recorded and replayed In spite of a PC based radar system, all essential information required for safe and efficient navigation of ship can be provided.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제13권6호
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• pp.2484-2490
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• 2012

This study reports on the development and performance verification of cell simulation boards of simulator and the embedded program for board control of the battery management system (BMS) of electric vehicle (EV) cars, which manages the next-generation automotive lithium-ion battery pack. Here, we have improved the speed of the simulator by using operational (OP) amplifier and transistors that were connected in series. In addition, using a digital analog converter (DAC) in each channel, we have improved the performance by channel-to-channel isolation (isolation) as compared to the traditional methods. Furthermore, by constructing a current-limiting protection circuit, one can be protected from disturbance and, by utilizing a precision shunt resistor for the current sensor, we have increased the precision of the current control. In order to verify the performance of the developed simulator, we have performed the experiment 10 times, with values ranging from 0.5 V to 5 V, and a voltage drop step of 0.5 V. Significance analysis of experimental data, and repeatability tests were performed, showing an average standard deviation of 0.001~0.004 V, indicating high repeatability and high statistical significance of the current method and system.