• Journal of the Korea Society for Simulation
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• v.11 no.2
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• pp.17-29
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• 2002

There is an increasing interest in high-performance A/D(Analog-to-Digital) converters for use in integrated analog and digital mixed processing systems. Pipeline A/D converter architectures coupled with BiCMOS process technology have the potential for realizing monolithic high-speed and high-accuracy A/D converters. In this paper, the design of 12bit pipeline BiCMOS A/D converter presented. A BiCMOS operational amplifier and comparator suitable for use in the pipeline A/D converter. Test/simulation results of the circuit blocks and the converter system are presented. The main features is low distortion track-and-hold with 0-300MHz input bandwidth, and a proprietary 12bit multi-stage quantizer. Measured value is DNL=${\pm}$0.30LSB, INL=${\pm}$0.52LSB, SNR=66dBFS and SFDR=74dBc at Fin=24.5MHz. Also Fabricated on 0.8um BiCMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.43-50
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• 2007

In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.173-176
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s for video applications. Proposed architecture is designed low power A/D converter that pipelined architecture consists of flash A/D converter. This architecture consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using $0.25{\mu}m$ CMOS technology The SNR is 76.3dB at a sampling rate of 10MHz with 3.9MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}0.5/{\pm}2$ LSB, respectively. The power consumption is 13mW at 10Msample/s.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.131-135
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• 1991

A quantization error model is suggested for analog to frequency(A/F) converter in strapdown inertial navigation system(SDINS),which is characterized by some white noise exciting the state variables. Also, effects on the performance of SDINS by analog to digital(A/D) converter and A/F converter are analyzed and compared via covariance simulation. As a result, A/F converter turns out to be superior to the A/D converter with respect to the induced navigation error and the difficulty in circuit realization. The quantization error model developed in this paper appears to be useful for optimal filter design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.6
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• pp.87-90
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• 1978

In previous VFC type A/D converter high linearity charateristics knave been achieved to several hundred kHz, and in the converter with maximum output frequency of several MHz, the conversion linearity is poor in upper frequency range. In this paper the problem of the extension of the output frequency to MHz range is studied in the following two view points: First, a tunnel diode VCO is used to increase the output frequency range to several MHz. Second, the linearity between the input voltage and the frequency of the output pulse is accomplished by using negative pulse feedback circuit. From the experimental results, it was followed that the linearity of the proposed converter was about 0.209 percent at the frequency of 3.7MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.