• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
• /
• pp.626-628
• /
• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

• 센서학회지
• /
• 제24권6호
• /
• pp.359-363
• /
• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
• /
• pp.950-953
• /
• 2003

In this paper, sigma-delta A/D converter for ADSL modems using oversampling technique is designed. Conventionally, the oversampling A/D converter is consist of opamps, switched capacitors, quantizers, infernal D/A converters, and decimation filters. 3-bit flash A/D converter, 3-bit thermometer-based D/A converters, and sub-blocks are used for high speed operation. HSPICE simulator and CADENCE tool are used for verification and layout of the designed modulator. The internal A/D converter and D/A converters are operated at 130 MHz. In design of decimation filter Matlab is used for calculating coefficients and ModelSim and VHDL are used for design.

• 융합신호처리학회논문지
• /
• 제8권3호
• /
• pp.205-210
• /
• 2007

본 논문에서는 고속으로 아날로그 신호를 디지털 신호로 변환하기 위한 Flash A/D 변환기를 설계하였다. 해상도는 6-Bit로 설계하였으며, Flash A/D 변환기의 단점인 전력손실과 칩의 면적을 줄이기 위하여 CMOS 트랜지스터의 원리인 Threshold Inverter Quantization(TIQ) 구조를 이용하였다. TIQ로 동작시키기 위한 CMOS 트랜지스터 크기는 HSPICE의 반복적인 시뮬레이션 결과로 결정하였다. Flash A/D 변환기의 변환속도를 낮추는 Encoder 부분은 ROM이나 PLA 구조를 이용하지 않고 속도와 소비전력에서 우수하지만 설계과정이 복잡한 Fat Tree Encoder를 사용하였다. 제조공정은 Magna 0.18um CMOS에 Full Custom 방식으로 설계하였다. 시뮬레이션 결과 1.8 V 전원전압에 최대소비전력은 38.43 mW이며 동작속도는 2.7 GSPS를 얻을 수 있었다.

• 한국통신학회논문지
• /
• 제40권4호
• /
• pp.613-618
• /
• 2015

본 논문은 2단 플래시 A/D 변환기를 이용한 저전력 CMOS 플래시-SAR(successive approximation register)A/D 변환기를 제안한다. 전체 회로 구조는 상위 2비트 고속 플래시 A/D 변환기, 하위 8비트 저 전력 SAR A/D 변환기로 구성되어서 데이터 변환 클럭 수를 감소시켜서 변환속도를 향상시켰다. 또한 하위 8비트를 SAR 논리회로와 커패시터 D/A 변환기를 이용하여 저 전력으로 회로를 설계하였다. 제안 된 A/D 변환기는 $0.18{\mu}m$ CMOS 공정을 이용하여 구현하였고 2MS/s의 변환속도를 갖으며 9.16비트의 ENOB(effective number of bit)이 측정되었다. 면적과 전력소모는 각각 $450{\times}650{\mu}m^2$와 $136{\mu}W$이고 120fJ/step의 FoM을 갖는다.

• 대한전자공학회논문지SD
• /
• 제41권8호
• /
• pp.67-74
• /
• 2004

이 논문에서는 Interpolation 구조를 이용한 3.3V 8-bit 500MSPS CMOS A/D 변환기를 설계하였다. 고속 동작의 문제를 해결하기 위해서 새로운 프리앰프, 기준 전압 흔들림을 보정하기 위한 회로, 평균화 저항을 제안하였다. 제안된 Interpolation A/D 변환기는 Track ＆ Hold, 256개의 기준전압이 있는 4단 저항열, 128개의 비교기 그리고 디지털 블록으로 구성되어 있다. 제안된 A/D 변환기는 0.35um 2-poly 4-metal N-well CMOS 공정이다. 이 A/D 변환기는 3.3V에서 440mW를 소비하며, 유효 칩 면적은 2250um x 3080um을 갖는다.

• 한국정보통신학회논문지
• /
• 제11권11호
• /
• pp.2100-2106
• /
• 2007

[ $0.25{\mu}m$ ] N-well CMOS 공정기술을 이용하여 전류 구동형 A/D 변환기 회로를 설계하였다. 설계된 회로도에는 트랜스컨덕턴스(transconductance), 선형 폴더(folder) 회로 및 1 비트 A/D 변환기로 구성되어 있다. 트렌스컨덕턴스 회로를 이용하여 입력전압을 전류로 변환시킨 후 변환된 전류신호를 이용하여 선형성이 매우 양호한 폴더 회로를 얻을 수 있었다. 폴더 회로를 다단으로 종속접속시킴으로써 n비트 A/D 변환기로 확장할 수 있다. 본 연구에서 설계된 A/D 변환기는 대략 25MSPS으로 구동할 수 있는 6비트 A/D 변환기 회로이다.

• 한국주조공학회지
• /
• 제23권5호
• /
• pp.235-243
• /
• 2003

The collapsibility of sodium silicate-bonded sands mixed with the L.D converter slag powder to form a hardener were investigated. Five to six percent sodium silicate on the basis of silica sand and 30-40% L.D converter slag powder on the basis of sodium silicate, were mixed and the compressive strength, surface stability index(SSI), bench time, retained strength of the standard sand specimens were measured. The properties were similar to those of general inorganic bonded self-setting molds. The compressive strength and surface stability index were increased and the retained strength and bench time were decreased with increased amount of the L.D converter slag powder. The retained strength of sodium silicate-bonded self-setting molds with the L.D converter slag powder were decreased than $CO_2$ sand molds. The collapsibility of sodium silicate-bonded self-setting molds with the L.D converter slag powder were superior in comparison with $CO_2$ sand molds. The L.D converter slag powder could be used as hardener and collapse agent for the sodium silicate-bonded self-setting molds.

• 반도체디스플레이기술학회지
• /
• 제3권4호
• /
• pp.19-27
• /
• 2004

The characteristic evaluation of A/D converter is to measure the linearity of the converter. The evaluation of the linearity is to measure the DNL, INL, gain error and offset error in the various test parameters of A/D converter. Generally, DNL and INL are to be measured by the Histogram Test Algorithm in the DSP-based ATE environment. And gain error and offset error are to be measured by the calculation equation of the measuring algorithm. It is to propose the new Concurrent Histogram Test Algorithm for the test of the housekeeping A/D converter used in the CDMA cellular phone. Using the proposed method, it is to measure the DNL, INL, gain error and offset error concurrently and to show the measured results.

• 한국초전도학회:학술대회논문집
• /
• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
• /
• pp.160-164
• /
• 2000

Digital to analog converters based on the Josephson effect are promising for voltage standard, because they produce voltage steps with high precision and good stability. In this paper, we made a simulation study on RSFQ D/A converter. RSFQ D/A converter was composed of NDRO cells, T(toggle) flip-flops, D flip-flops, Splitters and Confluence Buffers. Confluence Buffer was used to reset the D/A converter. We also obtained operating margins of the important circuit values by simulational experiments.