• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.201-204
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• 2000

In this paper, an A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s. This architecture is proposed using the 2-step architecture for high speed conversion rate. It is consisted of sample/hold circuit, low power comparator, voltage reference circuit and DAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.2$\mu\textrm{m}$ CMOS technology. The SNR is 45.3dB at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}$1 / ${\pm}$2 LSB, respectively. The power consumption is 13㎽ at single +2.5V supply voltage.

• Journal of Power Electronics
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• v.14 no.4
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• pp.649-660
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• 2014

A novel non-isolated bidirectional soft-switching SEPIC/ZETA converter with reduced ripple currents is proposed and characterized in this study. Two auxiliary switches and an inductor are added to the original bidirectional SEPIC/ZETA components to form a new direct power delivery path between input and output. The proposed converter can be operated in the forward SEPIC and reverse ZETA modes with reduced ripple currents and increased voltage gains attributed to the optimized selection of duty ratios. All switches in the proposed converter can be operated at zero-current-switching turn-on and/or turn-off through soft current commutation. Therefore, the switching and conduction losses of the proposed converter are considerably reduced compared with those of conventional bidirectional SEPIC/ZETA converters. The operation principles and characteristics of the proposed converter are analyzed in detail and verified by the simulation and experimental results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.421-425
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• 2008

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.05a
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• pp.177-181
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• 2002

In this paper, the design of 12bit pipeline BiCMOS A/D converter presented. A BiCMOS operational amplifier and comparator suitable for use in the pipeline A/D converter. The main features is low distortion track-and-hold with 0-300MHz input bandwidth, and a proprietary 12bit multi-stage quantizer.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.128-130
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• 2006

We introduce 2[MVA] 3300[V] 7-level voltage source inverter system developed by POSCON and describe the main characteristics of inverter system i.e. PWM converter, H-bridge power module, phase shifted carrier PWM The PWM converter is a three-phase boost converter, which operates in a 4-quadrant and in a nearly unit displacement power factor. Experimental waveforms are also presented to verify the proposed method and performance of the developed system.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.346-349
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• 2003

A SiGe HBT MMIC double balaced up-converter has been designed and fabricated for C-band WLAN applications. The up-converter is based on the Gilbert cell mixer with an active baluns for differential inputs of LO and IF signals. The designed up-converter exhibits a conversion gain 12.5dB for a -10 dBm LO power. It also exhibits LO-RF isolation of 19.3dBc, and IF-RF isolation of 23.3 dBc at a 1-dB compression point of -14.2dBm

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.3
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• pp.186-190
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• 2005

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics, 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB\~-0.63LSB$ and $0.53LSB\~-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.53-61
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• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.98-106
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• 1994

To realize high accuracy and high speed we developed a new self compensation scheme and applied it to a 10-bit D/A converter. This circuit can compensate the device mismatch without interrupting the D/A converter operation. With the compensation circuit,INA decreased down to 0.22LSB from 0.47LSB. The device was fabricated using a 0.8$\mu$m CMOS process. The area of the D/A converter core is 3.2mm$^{2}$ and the area of the compensation part is 0.64mm$^{2}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.367-373
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• 2001

A programmable A/D converter is designed with 8 N and P channel MOSFETs, respectively. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a 1.2 ${\mu}{\textrm}{m}$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10m Volt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, 37㎽ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.