A Low-Power 2-Step 8-bit 10-MHz CMOS A/D Converter

저전력 2-Step 8-bit 10-MHz CMOS A/D 변환기

  • 박창선 (전북대학교 전자정보공학부) ;
  • 손주호 (전북대학교 전자정보공학부) ;
  • 김영랄 (전북대학교 전자정보공학부) ;
  • 김동용 (전북대학교 전자정보공학부)
  • Published : 2000.06.01

Abstract

In this paper, an A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s. This architecture is proposed using the 2-step architecture for high speed conversion rate. It is consisted of sample/hold circuit, low power comparator, voltage reference circuit and DAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.2$\mu\textrm{m}$ CMOS technology. The SNR is 45.3dB at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}$1 / ${\pm}$2 LSB, respectively. The power consumption is 13㎽ at single +2.5V supply voltage.

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